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1 Day Arm 2007

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1 Day training for migrate from 8bit to ARM
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  • 1. Standard Microcontroller 1-day ARM TrainingPaolo Bernasconi NXP Semiconductors, FAE
  • 2. Agenda 9:30 LPC2000 Technical Training Part I - Introduzione - LPC2000 devices and roadmaps dev tools. I nuovi dispositivi della famiglia LPC2300 e LPC2400. Novità per il 2007☺ Break- Presentazione dell'Architettura ARM7 (mappa di memoria, systemcontrol, peripherals) 12:30 ☺ Pranzo 13:30 LPC2000 Technical Training Part II - Inizializzazione delle periferiche di sistema PLL, Vector Interrupt Controller e USB - presentazioni di esempi con tool Keil e scheda di valutazione Keil☺ Break - Implementazone dell’architettura ARM7 nella famiglia LPC23/24 - Q&A 17:30 ChiusuraCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 3. Standard Microcontroller Cores32/16-bit100 LPC3000 ARM926EJ Throughput LPC2000ARM7TDMI-S1016-bit XA 16-bit8-bit LPC900 2-Clock6-Clock MX LPC700 6-Clock C51X2 6-Clock 1 C51 12-Clock Memory Size2 KB64 KB1 MB >16 MB CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 4. NXP Embedded Flash Process RoadmapMature product line low-cost, 3-5V OTP 5V Flash familySi Foundry LPC900 Family3V FlashMOS34 / ASMCPlanned LPC2000 Family EmbeddedARM7S-TDMI Flash 1.8V FlashCMOS90 MOS34 / SSMCCrolles2ARM926EJ ARM1156EJCMOS90 CMOS65Crolles2 Crolles20.5μ 0.4μ 0.35μ0.18μ 0.16μ 0.14μ90n 65n Process Feature SizeCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 5. Standard Microcontroller Strategy Summary Develop Innovative and Cost Effective ProductsFocus on 16/32-bit market with wide rangeof ARM7 & ARM9 based products Expand the successful LPC Family approach: - New peripherals like USB, Ethernet, .......Use highly competitive flash based processes: - 0.35 μm and 0.18 μm Flash in production - Shrink path down to 0.14 μm - First products in 90nm in 2005Introduction of innovative packages:- Chip scale packages like HVSON10, TFBGA256CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 6. LPC2000 Family 16/32-bit ARM7TDMI-S Products
  • 7. ARM Microcontrollers NXP has developed a family of ARM-based MicrocontrollersFor - Low-Cost High Volume Applications With - Embedded Flash and SRAM - On-board AMBA-bus Peripherals (Adv. µC Bus Architecture) - Real-Time Deterministic behavior (no Cache required) -High performance NXP specific Flash Memory matrix -and access design - Full Debug, Real-time Monitoring and Trace facilities To - Continue on from our successful 8-bit 80C51 Family - Enable new low-cost 16/32-bit Microcontroller-based applicationsCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 8. NXP Standard MicrocontrollersThe Ultimate Products….. 13 mm LPC2000 LPC3000 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 9. History - NXP a leader in ARM NXP relationship with ARM Ltd. spans a decade– One of the three founding partners of ARM– Development with cores starting from ARM2 through ARM11 NXP offers the most experience– Over 250 ARM designs - more than anyone else in the industry– In Top 3 for ARM shipments worldwide– More than a dozen ARM cores in over 7 CMOS processes NXP is a long-term ARM licensee– Extensive license relationship provides continuous access to all architectures– Announcing off-the-shelf ARM microcontrollers with embedded Flash CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 10. ARM vs. other 32/16-bit Emb. Architectures 450 400 350ARM Volume in300 Y2004: 190 MU250M units200 150 100 50 M0K R -7 PS 68 AXSH MIPo XX PC 2020 2002080 C06 er 720 05R20 04 w 8620 03A 20 02 0119X SP+ 190 0 2099 98Source: SEMICO Research, Q4 2002 STNumbers excluding cell phone handsets ARM : Leading solution for Industrial / Automotive,Communications and General PurposeCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 11. Shipments of all ARM products Million USD Revenues of ARM Holdings PLC M Unit Shipment of ARM based productsARM’s partners shipped 1,662 Mpcs in 2005 (+31%)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 12. ARM7TDMI-S NXP ChoiceThe ARM7TDMI-S is based on an ARM7 coreT- Thumb architecture extension • ARM Instructions are all 32 bit • Thumb instructions are all 16 bit • Two execution states to select which instruction set to execute D- Core has debug extensionsM- Core has enhanced multiplierI- Core has Embedded ICE MacrocellS- Fully synthesis ableCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 13. 2007 16/32-bit ARM7 LPC2000 Released (28) UART(2), I2CUART(4) SPI/SSP, LV RTC H2 ’06 2x AHB + EthernetADC(1-2), DAC +Single p supply3V single p.supply3.3V/01 H1 2007Flash SecurityMinibusUART(2), I2CUART(2), I2C, USBSPI(2), RTCSPI/SSP, LV RTC100 - 144 pins ADC, CAN LPC21xx ADC(1-2), DACARM7TDMI-S : LPC2000 UART(4), I2C(3)Flash Security 3V p.supply UART(2), I2CSPI(1), SSP(2), CAN(2)ARM926EJ : LPC30001.8V and 3.3 V Flash Security SPI(2), RTCLV RTC, ADC, DAC,10b-ADCPWM(2), LPC2148+external busLPC2194 /01 LPC2138 /01 Flash Security USB fullI2C 512K/32K+8K UART(2),+ USB256K/16K 512K/32K 1.8V and 3.3 V UART(2), I2C10/100 Ethernet,USB SPI(2), RTCOTG/Host CAN (4)ADC(2), DAC + external bus CAN(2), IRCADC(2), DACSPI(2), RTCADCADC, CAN 180 - 208 pins LPC2378 1.8V and 3.3 VLPC2146LPC2129 /01 LPC2136 /01LPC2214 /01 Flash Security UART(4), I2C(3) 512K/58KLPC2106 /01 256K/32K+8K SPI(1), SSP(2),256K/16K 256K/16KEthernet, 256K/32K1.8V and 3.3 V 128K/64K USB LV RTC, ADC CAN (2)USB, CAN,ADC(2), DAC+external busADC(2), DAC ADC, DAC, MiniBus, MMC Floating+ externalPWM(2), LPC2368 pointbus LPC2144 USB-OTGLPC2124 /01 LPC2134 /01LPC2212 /01LPC2294 /01512K/58K coprocessor LPC2105 /0110/100 Ethernet, 16 bits codec128K/16K+8K256K/16K 128K/16K128K/16K256K/16K Ethernet, USB Host fullUSB 128K/32KUSB High CAN(2), IRC,ADC(2), DACADCADC CAN (4)USB, CAN, speedADC(2), DAC External Bus speed deviceMMC LPC3190LPC2366 LPC2468 LPC2142LPC2119 /01 LPC2888LPC2132 /01LPC2220LPC2292 /01 LCD int256K/58K512K/98K LPC2104 /01 64K/16K+8K128K/16K 1M/64K 64K/16K0K/64K 256K/16KIIS,SPIEthernet, Ethernet,USB 128K/16KUSB HSADC, DAC ADC CAN (2)CAN (2) EthernetADC, DACUSB, CANUSB, CAN LPC2364 LPC2458 LPC2141 LPC2101/2/3LPC2114 /01LPC2210 /01LPC2880LPC3180LPC2131 /01 LPC2290 /01128K/34K512K/98K 32K/8K+8K8/16/32K/Flsh128K/16K 0M/64K 64K RAM, 32K/8K 0K/16K0K/16KUSB Ethernet, Ethernet, 2/4/8KRam USB HS 32+32K CacheADCADCCAN (2)ADC ADCADC,LV,RTCUSB, CANUSB, CAN180 pins 48pins 320 pins64pins 64pins 64pins 144pins 144pins Flex. Suppl. UART(2),ADC, 2xI2C, UART(2), I2CUART(2), I2CUART(2), I2C UART(2), I2CUART(2), I2CHS USB,I2C(2), SPI, 2xSPI, SPI(2), RTCSPI, SPI/SSP,SPI(2), USB, SPI(2), RTC SPI(2), RTC Flex. Ext. SPI/SSP, RTC,7xUART,USB-ADC, CAN LV RTCLV RTCADC ADC, CAN(2/4)Mem.ADCOTG.ADC(1-2), DAC ADC, DACLCDcontr.Interf .Timing/features/packages of non released parts mayCONFIDENTIAL change without prior notificationSubject/Department, Author, MMMM dd, yyyy
  • 14. Roadmap – 32-bit portfolio Roadmap Recently releasedLPC31xx: ARM9• SPI LPC3190• IIS interface LPC3000LPC3000• Ethernet MAC controller FunctionalityLPC3000• LCD interface LPC3000 LPC24xx: ARM7 • Ethernet (MII+RMII) LPC2000 LPC2000 • USB FS DeviceLPC2468 LPC2000 LCD • USB Host/OTG LPC2458LCDLCD • 2 x CAN LPC2368 LPC2378 • Ext. Memory (SDRAM, SRAM) • 96K SRAMLPC23xx: ARM7 LPC2366 • Ethernet (RMII)• USB FS Device LPC2364• 2 x CAN Recently released LPC22xx/01New releases LPC21xx/01LPC210x/01Feature and performance improvements 2007Time CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 15. /00 Versions Status PartsSamples StatusLPC2104FBD48/00YesRFSLPC2105FBD48/00YesRFSLPC2106FBD48/00YesRFSLPC2106FHN48/00YesRFSLPC2114FBD64/00YesRFSLPC2124FBD64/00YesRFSReset.1 bug fixed LPC2119FBD64/00YesRFSLPC2129FBD64/00YesRFSLPC2104/00 and LPC2105/00 are LPC2194HBD64/00YesRFSIndus. Temp. range qualifiedLPC2212FBD144/00 YesRFSLPC2214FBD144/00 YesRFSLPC2292FBD144/00 YesRFSLPC2292FET144/00 YesRFSLPC2294HBD144/00 YesRFSCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 16. /01 Versions Status PartsSamplesStatus RFS date LPC2104FBD48/01NoDev H1/07 LPC2105FBD48/01NoDev H1/07 LPC2106FBD48/01NoDev H1/07 LPC2106FHN48/01NoDev H1/07 LPC2114FBD64/01NoDev H1/07 • All bugs corrected excepted core.1LPC2124FBD64/01NoDev H1/07 LPC2119FBD64/01NoDev H1/07 LPC2129FBD64/01NoDev H1/07 • Some enhanced features: LPC2131FBD64/01Yes RFS Now LPC2132FBD64/01Yes RFS NowFast I/O (3-4 times faster than LPC2132FHN64/01Yes RFS Now standard) LPC2134FBD64/01Yes RFS NowCounter inputs LPC2136FBD64/01Yes RFS NowDedicated result registers per ADC LPC2138FBD64/01Yes RFS Now input LPC2138FHN64/01NoRFS NowUART improvementsLPC2194HBD64/01NoDev H1/07Program security (for the LPC210x) LPC2210FBD144/01 Yes RFS Now LPC2290FBD144/01 Yes RFS Now… LPC2212FBD144/01 NoDev H1/07 LPC2214FBD144/01 NoDev H1/07 LPC2292FET144/01 NoDev H1/07 LPC2294HBD144/01 NoDev H1/07CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 17. LPC2104/5/6 Block Diagram RST RTCK Vdd TRST 128 KB16-64KBVss 128 KB16-64KB TMS TDO TCK X1X2 TDI FLASH SRAMFLASH SRAM SystemSystemTest/DebugTracePLLTracePLLFunctionsFunctions SRAM MemorySRAM MemoryController Accelerator System ClockController AcceleratorAHB BridgeAHB BridgeARM 7TDMI-S Local BusARM 7TDMI-S Vectored Interrupt Vectored InterruptController Real Time WatchdogController Real Time Watchdog AHB to VPB Bridge AHB to VPB BridgeClock Timer Clock Timer VLSI Peripheral Bus (VPB) 2 II2CC GPIOSPI PortTimer0Timer1 PWM UART0 UART1GPIOSPI PortTimer0Timer1 PWM UART0 UART1MAT0.0-2 MAT1.0-3CAP1.0-3 PWM1 - 6CAP0.0-2 2 pins 8 pinsGPIOSSEL MOSI SCLMISOSDASCKCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 18. LPC2101/2/3 Blocks 2/4/8Kb 8/16/32Kb FLASH FLASHSRAM Fast GPIOSRAM Bootloader, TRST RealMonitor TMS TCKTDO TDI VectoredVectored InterruptInternal FlashSRAMInterrupt Fast Internal Flash SRAM Fast EICEETM Controller ETM GPIO Controller ControllerController GPIO Controller Controller Local Bus AHB BusARM 7TDMI-SARM 7TDMI-SARM Local BusAHB Bus RST SystemSystemFunctionsFunctions AHB to VPBX1 AHB to VPBPLLX2 BridgePLLBridge Real Time Watchdog Real Time Watchdog VbattClock Timer Clock TimerRTCX1RTCRTCX2Osc VLSI Peripheral Bus (VPB) Timer0 Timer1 Timer2 Timer3ADC Timer0 Timer1 Timer2 Timer3 ADC 2 x I22C2 x IC SPI SPI/SSP UART0UART1 GPIOSPI SPI/SSP UART0UART1 GPIO 10-bits 32-bit 32-bit 32-bit32-bit 16-bit 16-bit10-bits16-bit 16-bit4 x MAT3 3 x MAT0 3 x MAT2 4 x MAT13 x CAP03 x CAP24 x CAP1 8 InputsGPIO2 pins 8 pins AVDDAVSSSSEL SSEL MOSI MISO MISOMOSI SDA SCL SCK SCKCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 19. *Flash size: 128KB LPC2119Package: LPC2119, LPC2129,LPC2194256KB LPC2129,94 LQFP64 RSTVdd16KB128/256KB* Vss 16KB 128/256KB* X1X2 JTAG 610 RT-TraceSRAMFLASHSRAMFLASH SystemSystemE-ICEETM PLL ETM PLLFunctionsFunctions SRAM Flash ControllerSRAMFlash Controller ARM 7TDMI-S ARM 7TDMI-SController // MAM System ClockControllerMAMAHB BridgeAHB BridgeARM Local Bus AHB BusVectoredAHB to VPB Vectored AHB to VPBInterrupt Bridge Real TimeWatchdog InterruptBridge Real TimeWatchdogControllerClockTimerController ClockTimerVLSI Peripheral Bus (VPB)2II2C CGPIOSPI Port Timer0 Timer1 PWM CAN1CAN210-bit ADC UART1UART0 GPIOSPI Port Timer0 Timer1 PWM CAN1CAN210-bit ADC UART1UART0 MAT0.0-3CAP1.0-3 AIN0 - 3 MAT1.0-3PWM1 - 6 CAP0.0-38 pins 8 pins GPIO SSELMOSISCLMISO SDA SCK RD2 TD1 RD1 TD2CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 20. LPC2292, LPC2294 n: LPC2292 = 2 144-PinLPC2294 = 4 Packages 16KB256KB16KB256KB RST Vdd VssX1 X2JTAG6 10 RT-Trace SRAMFLASH SRAMFLASHBLS3:0 CS3:0A23:0D31:0 WE OESystem System E-ICE ETM ETM Functions Functions SRAM Flash Controller External MemorySRAMFlash Controller External MemoryARM7TDMI-SARM7TDMI-SController // MAM ControllerControllerMAMController System PLL PLL Clock AHBAHB Bridge Bridge ARM Local Bus AHB Vectored Interrupt AHB to VPBReal TimeWatchdog Vectored Interrupt AHB to VPBReal TimeWatchdog ControllerBridge ClockTimer Controller BridgeClockTimer VPB ...2 II2CCGPIOSPI0SPI1 Timer0Timer1 PWMCAN1 CANnUART1 UART0 10-bit GPIOSPI0SPI1 Timer0Timer1 PWMCAN1 CANnUART1 UART0 10-bitADC ADCMAT1.0-3 CAP1.0-3MAT0.0-3 CAP0.0-3PWM1 - 6AIN0 - 78 pins8 pins4 pins 4 pins GPIO SCLSDA RDn TDnRD1 TD1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 21. LPC2220 Flashless 72 MHz RTCKRSTVddTRST 16KB //64KB Vss 16KB 64KB TMS TDO TCKX1 X2 TDISRAM 0/128/256 KBSRAM0/128/256 KBFLASH FLASHSystem SystemTest/DebugTrace PLLTrace PLLFunctions Functions SRAMSRAM ARM 7TDMI-S Memory ARM 7TDMI-S MemoryController System ClockController AcceleratorAcceleratorAHBLocal Bus CS 3:0A 23:0 VectoredExternal AHB to VPB BridgeVectored External AHB to VPB BridgeBLS 3:0 Interrupt Memory Real Time Watchdog InterruptMemory Real Time Watchdog OE,WE Controller ControllerClock TimerController ControllerD 31:0 Clock Timer VLSI Peripheral Bus (VPB) 0/2x2 II2CCTimer0Timer1 PWMUART0 UART1ADC2xSPI/SSP GPIO 0/2xTimer0Timer1 PWMUART0 UART1ADC2xSPI/SSP GPIOCANCAN CAP1.0-3PWM1 - 6MAT0.0-2 MAT1.0-3 CAP0.0-2 8 pins2 pins8 pinsSSEL SCLSDA MOSIMISOSCKGPIOPackage: LQFP144 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 22. LPC213x Block DiagramRSTVdd32…512 KBTRST 8…32KB RTCKVss32…512 KB 8…32KB TMS TDO TCKX1 X2 TDIFLASHSRAMFLASHSRAM SystemSystemTest/DebugTrace PLLTrace PLL FunctionsFunctionsSRAM Memory SRAM Memory ARM 7TDMI-S BrownOutDetect ARM 7TDMI-S BrownOutDetect Controller AcceleratorSystem Clock Controller Accelerator PowerOnResetPowerOnReset Local Bus and AHB AHB to VPB Bridge Vectored Interrupt AHB to VPB Bridge Vectored Interrupt 32 kHzController Real TimeWatchdog Controller Real TimeWatchdogVbatClockTimer ClockTimer VLSI Peripheral Bus (VPB)Timer0 Timer1PWM UART0 UART1 ADC0/1 DAC GPIO SPI Port SSP Port 2 2x II2C 2x CTimer0 Timer1PWM UART0 UART1 ADC0/1 DAC GPIO SPI Port SSP PortCAP1.0-3PWM1 - 6 MAT0.0-2 MAT1.0-3 CAP0.0-2 2x8 pins1-10-bit8 pins2 pinsSSEL SSELMOSI SCL MISOMISO SDA MOSI SCKGPIOSCK LPC2131, LPC2132NOT Package: LQFP64/HVQFN64 ONLY ONE LPC2131 CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 23. LPC213x Series Overview 60 MHz Operation (54MIPS)from both on-chip Flash and SRAM2 I2C, 2 UARTs, 1 SPI, 1 SPI/ SSPTwo 8-channel 10-bit ADCsOne 10-bit DAC4 Timers (Capture/Match/PWM/WDT)47 I/O pins (5V tolerant)3.3V Single-Voltage Supply32KHz RTC, BOD, PORUser-code securityReal-time Debugging & Trace * Available Q1 2005ISP, IAP, Parallel Programmer SupportTiny Packages: QFP64 (10 x 10 x 1.4 mm), HVQFN64 (9 x 9 x 0.85 mm)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 24. LPC213x Series OverviewSingle Supply Voltage• 3.3V Single-Voltage Supply• CPU operating voltage range of 3.0V to 3.6V (3.3V +/- 10%) with 5 Volt tolerant I/Opads. Brown Out Detection (BOD @ 2-stage monitoring of the voltage)• Stage 1: Vdd < 2.9V, the Brown-Out Detector (BOD) asserts an interrupt signal to theVIC (Vectored Interrupt Controller).• Stage 2: Vdd < 2.6 V LPC213x will be reset to prevent alteration of the Flash asoperation of the various elements of the chip would otherwise become unreliable due tolow voltage. Power On Reset (POR)• The BOD circuit maintains this reset down below 1V, at which point the Power-On Resetcircuitry maintains the overall Reset. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 25. LPC213x Series Overview RTC with additional crystal pinsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 26. LPC213x Series Overview RTC:• Can be clocked by a separate 32.768KHz or by prescaler divider based on VPB clock • So RTC can run in Power Down mode • Has got its own supply pin Vbat which can be connected to battery or to the (2.0… 3.3… 3.6 V) supply. • Typical power consumption is 14-20uA (@25 degree, with Vbat 2.5 to 3.6V respectively) when the device is in Power Down ModeCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 27. LPC2142/44/46/48 Block DiagramRSTVdd64-512 KB TRST 16-32KBVss64-512 KB 16-32KBTMSTDOTCK X1X2TDI FLASHSRAMFLASHSRAM PLL11 PLLSystem ClockSystem SystemTest/Debug ETM ETM Functions Functions PLL22 PLL USB ClockSRAMMemory SRAMMemory ARM 7TDMI-S BrownOutDetectARM 7TDMI-S BrownOutDetect ControllerAccelerator ControllerAccelerator VIC VICPowerOnReset PowerOnReset Local Bus AMBA AHB BusD+ 8 KB SRAM8 KB SRAMAHB to USB 2.0 FullAHB toD-USB 2.0 Full 32 kHz shared w/ DMAshared w/ DMA VPB Speed Device Up_LED OR VPB Speed Device Real TimeWatchdog Real TimeWatchdog(LPC2148 only)Connect (LPC2148 only)Bridge Vbatw/ DMABridgew/ DMAClockTimer ClockTimer VbusVLSI Peripheral Bus (VPB) UART0/12 II2C0/1C 0/1 Timer0/1 PWMADC 0/1DACSPI Port SSP Port UART0/1Fast I/OTimer0/1 PWMADC 0/1DACSPI Port SSP Port Fast I/O PWM1 - 6 Tx/RX 0,1pins (6)Modem CAP x 8MAT x 86+8 pins 1-10-bit SSELSSEL MOSI SCLMISO MISO SDAMOSISCK GPIO 46 max SCK Has 1.8V Regulator. Only 3V input needed64-pin LQFPCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 28. LPC214x Series Overview 60 MHz Operation from both on-chip Flash and SRAM Spec LPC2142 LPC2148 2 I2C, 2 UARTs, 1 SPI, 1 SPI/ SSP Up to 14-channels 10-bit ADCs Internal 64 KB 512 KB One 10-bit DAC Flash 4 Timers (Capture/Match/PWM/WDT) Internal 16 KB 32 KB + 8 45 I/O pins (5V tolerant) SRAM KB shared – 3.5 times faster than older I/O! 10-bit ADC 1 x 6-chan1 x 8-chan 3.3V Single-Voltage Supply 32KHz RTC with Vbat input1 x 6-chan Brown Out Detect, Power On ResetUARTs2 x 16C550 2 x 16C550 User-code security (one with autoCTS/RTS plus Real-time Debugging & Tracefractional baud ISP, IAP, Parallel Programmer Supportrate divisor) Tiny Packages: LQFP64 (10 x 10 x 1.4 mm), HVQFN64 (9 x 9 x 0.85 mm) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 29. LPC214x - USB Features USB 2.0 Full Speed DeviceSupports 32 physical (16 logical ) endpoints – Supports Control, Interrupt, Bulk and Isochronous endpoints2kB of endpoint RAM for communication only (not general purpose)8kB block of general purpose SRAM usable by USB DMA (LPC2148only)USB controller has dedicated PLL (functionally same as other PLL)USB registers are accessed via the VPB bus, but the 8kB block isaccessible via the AHB busCustomer can choose between the UP_LED (Good LinkTM) OR theCONNECT (Soft ConnectTM) functionalityCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 30. Extending the success to LPC214x LPC213x Features: • Fast Embedded Flash: Up to 512K Bytes of nearly 60 MHz zero wait state execution from 128-bitx2 wide Flash with Memory Acceleration • Single-voltage supply: on-chip DC-DC converter takes a single 3.3V supply with POR and BOD capabilities • Many standard peripherals: Real-time-clock with power domain, SPI, I2C, UARTS, TimersLPC214x Adds: • USB 2.0 Full-speed 12 Mbits/sec with full USB standard compliance and DMA• Fast I/O Capability; speeds up Software controlled I/O by 3.5X, up to 15Mhz port-pin toggling frequency• 2 10-bit ADCs and a 10-bit DAC with individual result registers• Enhanced UART with hardware handshake plus fractional baud rate divider. -> crystal frequency can be set to a independent value of to the baud rate generator clockCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 31. 2 10-bit Analog-to-Digital Converters with: • 400 Kbits/Sec Sampling frequency with 8 Channels• Each Channel has its own Result Register thus reducing CPU Interrupt Overhead by a factor of 8• ADCs can Operate in Burst Mode with autonomous signal acquisition• ADCs can be synchronized (e.g. for simultaneous current & voltage measurement) and triggered by an input pin or Timer matchADC Inputs ADC Clock(CLKS Bits)1-8n-bit ADCSelect Multiple Channels Input Scan ADCR (7:0) (n Clocks/Conv)(SEL Bits)… ADDR7 ADDR0 ADDR1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 32. NXP USB versus CompetitionUSB Standard PhilipsAtmel SAM7S64ST STR71X Bi-directional* Endpoints supported 16 max/device16 4 8Modes SupportedControl,Control, Control,Control,Interrupt,Bulk, Interrupt,Bulk,Interrupt,Bulk, Interrupt,Bulk, Isochronous IsochronousIsochronous IsochronousMax. Control Buffer size.64 bytes64 bytes 64 bytes64 bytesMax. Interrupt Buffer Size 64 bytes64 bytes 64 bytes64 bytesMax. Bulk Buffer Size64 bytes64 bytes 64 bytes64 bytesMax. Isoch. Buffer Size 1023 bytes1023 bytes64 bytes 512 bytesDMA CapabilityYesNoNo* Separate input/outputCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 33. LPC2880/8 Family for MP3 player and audio management best fit
  • 34. LPC2880/88 Blocks 180 pinsBootSRAM BootSRAMFLASHFLASHROM ROM 1MB 64k(1) TRST TMS TCK TDOSEL TDIVectored VectoredExternal Static MemoryInterrupt ROMSRAM Internal FlashInterrupt ROM SRAM Internal FlashController E-ICEController Controller Controller ControllerController Controller Controller Controller(SDRAM/Flash/SRAM) Local BusAHB BusARM 7TDMI-SARM 7TDMI-S ARM Local BusAHB Bus 8KB Cache 8KB Cache System Functions HS USBRSTSystem Functions HS USB BO, With BO,PLL-With PORGP DMA AHB to APB PORsysDMAGP DMAAHB to APB DMAX1 ControllerBridges 0, 1, 2, 3PLL- ControllerBridges 0, 1, 2, 3 PLL-X2Real Time WatchdogReal Time WatchdogUSB USB Clock TimerClock TimerRTCX1 RTCRTCX2 OscVLSI Peripheral Bus (VPB)(VPB) UARTUART 16bit I²SADC GPIOSD/MMC 16bitI²S ADC GPIOSD/MMC I22LCDC SPITimer0Timer1PWM WithLCDICSPITimer0Timer1PWM CODEC With In/Out10-bits 85x card CODECIn/Out 10-bits85x card 2x IrDA IrDA Stereo audio out Stereo audio inPWM1 - 6 MAT1.0-3 MAT0.0-3CAP0.0-3CAP1.0-3LCD Bus DATO, BCKO, DCLKO,WSO 4 Inputs BCKI, WSITxd, RxdRTS, CTS MD[3:0]MCLK SSEL SCKMOSI MISOGPIODATI SDASCLLPC2888 only(1)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 35. LPC2800 Family Advanced and Flexible Memory Capability: On-chip: 1Mbyte of Flash, 64KB of RAM, and 32KB of ROM External Memory Controller for SDRAM, NOR and NAND Flash, and SRAM 8KBytes of Cache for enhanced performance from external memory LPC2800 Peripherals: 480 Mbits/sec High-Speed USB device with on-chip PHY Multi-Media Card, I2S, and LCD controller interfaces General Purpose DMA ATA interface LPC2800 Power Supply sub-systems: On-chip High-efficiency Switching regulator and Linear Regulators allow: Operation from single AA(A) Battery cell (0.9 to 1.6V) Operation from 5V USB input CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 36. LPC2800 Key Features (1)On-chip 1Mbyte of flash on LPC2888 (0Kbyte on LPC2880), 64Kbyte RAM, 8Kbytes cacheBoot ROM allow execution of Flash Code, external code, or flash programmingvia USBExternal Memory Controller for SDRAM, NOR and NAND flash and SRAM.8Kbyte of cache for enhanced performance from external memory.480 Mbits/sec High-Speed USB with on-chip PHYLCD Interface glue logic8 channels General Purpose DMA, (can be connected to the LCD interface too)SD/MMC Card Interface10Bit A/D converter + 16 Bit A/D and DA converters with amplification and gaincontrolUART with fractional baud rate generator, IrDA IIC and IIS interfaces CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 37. … LPC2800 Key Features (2) Innovative Event Router allows interrupt, power-up- and clock startcapabilities from up to 107 sources. Each signal can act as an interruptsource, or a clock enable or reset source for the LPC2880/88 modulesAdvanced clock generation: CPU clock can be obtain from the RCT32Khz clock nowIntegrated DC/DC converter can generate all required voltages from asingle battery or from USB powerCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 38. LPC2300/24000 Families 32-bit ARM7 Products
  • 39. Block Diagram LPC23xx/24xx (1/2)Signals TRST Trace Xtal1 Xtal2TDOTMS RSTTCKTDISystemTest/Debug Interface 64 KB512 KB Emulation TracePLL Functions SRAMFlashModuleARM7TDMI-SSystem Internal RC ClockOscillator Internal InternalSRAM Flash A[23:0],Controller ControllerD[31:0],Vectored External 16 KB etc.InterruptMemory ARM7 Local BusSRAMController ControllerAHB AHBBridgeBridgeAHB2 AHB1MII D+, D-, AHB toEthernet USB withorMasterSlave16 KB GP DMAetc. Port AHB Bridge RMII PortMAC with 4KB RAMSRAMController DMA& DMA APBAHB toDivider APB Bridge APBCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 40. Block Diagram LPC23xx/24xx (2/2)APB RXCLK, TXCLK EINT3:0External Interrupts RXWS,TXWS *I2S Interface RXSDA,TXSDA4 x 4 x CAP Capture / CompareSCK04 x 4 x MATTimers 0, 1, 2, 3MOSI0SPI, *SSP0 Interface MISO02 x 6 x PWM(no DMA on SPI)FS/SSEL02 x 4 x CAPPWM0, 12 x 4 x MAT SCK1 MOSI1*SSP1 Interface P0,1,...MISO1 General Purpose I/OFS/SSEL1Ain7:0MCICLK, MCIPWRA/D Converter*SD/MMC CardMCICMD, MCIDAT3:0 InterfaceAoutD/A Converter TxD0,2,3UART0, 2, 3 RxD0,2,3 VbatTxD12 KB Battery RAMPower Domain 2 RxD1 X1UART1DTR, RTS RTCReal Time Clock X2 OscillatorDSR, CTS, DCD, RI AlarmRX2, 1Watchdog TimerCAN Channels 1, 2 TX2, 1SCL0, 1, 2I2C Interfaces 0, 1, 2 System Control SDA0, 1, 2 * : Peripherals supported by the GP DMA ControllerCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 41. Features: Core72 MHz ARM7TDMIAdvanced Vectored Interrupt Controller (32 vectors, 16 priorities)Single 3.3V power supply (3.0V to 3.6V).– On-chip DC/DC converter for internal 1.8V4 reduced power modes, Idle, Sleep, Power Down, and Deep Power Down.– Processor wakeup from Power Down mode via any interrupt able to operate duringPower Down mode (includes external & GPIO interrupts, RTC, Ethernet wakeup).On-chip Power On Reset, and Brownout detectwith separate thresholds for interrupt and forced reset.On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.4 MHz internal RC oscillator that is the default system clock.On-chip PLL allows CPU operation up to the maximum CPU rate without theneed for a high frequency crystal. May be run from the main oscillator, theinternal RC oscillator, or the RTC oscillator.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 42. System Architecture Issues Challenges to preventing bottlenecks:• Ethernet requires support of 2 concurrent 100Mbits/sec data streams with up to 1500 byte packets• USB & Ethernet Streams are asynchronous and must both be supported including Isochronous mode USB (1024 byte data bursts)• CAN, SPI, SSP, I2C, SDIO, I2S, UARTs, Timers, PWMs, ADC, DAC, etc, must also be supported but these are all lower bandwidth with smaller packet sizes than Ethernet & USB (increases MCU core involvement)• CPU, Ethernet, and USB clock domains (72, 25/50, and 48 MHz) are all separate and need to communicate through memory• Multi-ported memory is expensive, complex, and not desirable42CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 43. The Goals of the LPC2300 FamilyPreventing overflow, underflow, and contention:• Manage multiple Asynchronous high-speed channels with no channel performance bottlenecks • Provide Ethernet, USB, CAN, UART, SPI, I2S, and I2C channels • Offer a one chip system for high performance and low power at a low cost • Include industry-leading Embedded Flash operating at SRAM speeds combined with ECC (error correction) for the best performance and power, security and reliability • Develop a large derivative family in different packages and with different capabilities and memory configurations at different price points, but allowing for easy transitions between family members (preserve code re-use)43CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 44. Building the LPC2300 – CPU & Memory ARM7TDMI-S Processor – 72 MHz Up to 512 KB Flash on-chip Flash – zero wait-state (execute code from Flash or SRAM) – 128-bit wide bus with patented Memory Accelerator Module (MAM) – 8-bits Error Correction Code (ECC) for every 128-bit word – Automotive qualified Flash process for high reliability Up to 58 KB on-chip Static RAM (all portions accessible by CPU and DMA)– 8 KB – 32 KB SRAM exclusively for CPU– 16 KB for Ethernet buffering– 8 KB for USB device (code or data)– 2 KB for RTC is for data only– Additional 4 KB USB FIFO buffer Advanced Vectored Interrupt Controller (VIC) – 32 IRQ sources Emulation Trace Module supports real-time trace Low power - 4 reduced power modes including Deep Power DownStart with the best embedded Flash in the market 44 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 45. Bus Bandwidth required for Industrial network SDRAM/SRAM/NOR interface Micro USB and SDIO for storage andwith peripheralsEmbedded Ethernet Connection toFlash Backbone and Local CAN Device Cluster Remote Networks Bus bandwidth usage at 72 MHz Peripheral AHB Bus Cumulativebandwidth % AHBSensors, Actuators, Drives, Switches etc.Bandwidth Ethernet 5050• More than 60% usage of bus USB4 54bandwidth causes collisions Ext, DRAM2074• Loaded system bandwidth at SSP4 7972Mhz is 96% for applicationConclusion: I2C(2) 2 81 1 AHB Bus is not sufficient CAN (2)3 84Multiple Busses and concurrent UARTS(2) 4 88DMA processing is required ADC8 96 45 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 46. Building the LPC2300 – Dual AHB BusTwo separate but not isolated AHBs – Any bus can still reach any other bus through bridges when neededHigh-bandwidth peripherals on different AHBs will not overwhelm the CPU orother peripheralsSignals TRST TraceTDOTMSTCKTDITest/Debug Interface 64 KB512 KB Emulation Trace SRAMFlashModuleARM7TDMI-S Internal InternalSRAM FlashController ControllerVectored 16 KBInterrupt ARM7 Local BusSRAMControllerAHB AHBBridgeBridgeAHB2 AHB1 AHB toMasterSlave16 KBPort AHB BridgePortSRAM APBAHB toDivider APB BridgeNo communications “traffic jams”!!46 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 47. The LPC2300 Advantage - parallel buses Concurrent operations become possible: • Ethernet packet reception and transfer to SRAM • CPU Instruction Fetch • USB packet reception and transfer to SRAMDedicating AHB Bus to Ethernet is required to guarantee 100 Mbits/sec Ethernet throughput without contention with other peripherals SignalsTRSTTrace Xtal1 Xtal2 TDO TMSRST TCKTDISystem Test/Debug Interface32 KB512 KBEmulation TracePLL FunctionsSRAMFlash Module ARM7TDMI-S System Internal RC ClockOscillatorInternal Internal SRAM Flash Controller ControllerVectored8 KBInterrupt ARM7 Local Bus SRAMControllerAHBAHBBridge BridgeAHB2 AHB1 D+, D-,AHB to EthernetUSB withMaster Slave 16 KBGP DMAetc. Port AHB BridgeRMIIPort MAC with4KB RAM EthernetSRAM Controller DMA& DMA APB AHB toDividerAPB Bridge USB APB47CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 48. Features: I/O Peripherals160 GPIO pins, all implemented as fast GPIOs, with 64 GPIO interrupts (plus 4other external interrupts).10 bit A/D Converter with input multiplexing among 8 pins.10 bit D/A converter.Four general purpose Timers with capture inputs, compare outputs, andexternal count inputs.Two linkable PWM / Timer blocks with support for 3 phase motor control withquot;dead timequot;. Each PWM has an external count input.Real Time Clock with separate power pin, alarm output, and 2K SRAM.Watchdog Timer. The watchdog timer can be clocked from the internal RCoscillator, the RTC oscillator, or the APB clock. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 49. Features: Serial Interfaces Ethernet MAC with associated DMA controller.These functions reside on an independent AHB bus.USB Device, Host (OHCI compliant), and OTG block with on-chipHost/Device PHY and associated DMA controller.Four UARTs with fractional baud rate generation, one with modemcontrol I/O, one with IrDA support, all with FIFO.CAN controller with two channels.SPI controller.Two SSP controllers, with FIFO and multi-protocol capabilities. One isan alternate for the SPI port, sharing its interrupt and pins.Three I2C Interfaces. The second and third I2C interfaces areexpansion I2Cs with standard port pins rather than special open drainI2C pins.I2S (Inter-IC Sound) interface for digital audio input or output.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 50. Power Options Power options: – On-chip DC-DC converter supplies 1.8V power to all internal logic, except in the RTC power domain. – 1.8V power can be supplied from off-chip for some pinouts.Power reduction modes: – Idle mode. – Power Down mode. – Sleep mode. – Deep Power Down mode.Power reduction modes are entered via an encoding of the IDL and PDbits in PCON, plus an additional new power control bit.CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 51. Idle Mode CPU is halted, reducing power used by:– The CPU itself.– Memories and their controllers used by the CPU.– Internal buses used by the CPU.Peripheral clocks and functions continue to run.All registers and memories retain their state.Wakeup from any enabled interrupt, or Reset.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 52. Sleep Mode All clocks are stopped to the CPU and peripherals.If enabled, the main oscillator and PLL are shut down.– All dynamic operation of the device is suspended.– The DC-DC converter remains operational.– The Flash memory remains on, allowing for fast wakeup.All registers and memories retain their state.Wakeup from any enabled interrupt that can occur without clocks, orReset. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 53. Power Down Mode All clocks are stopped to the CPU and peripherals.If enabled, the main oscillator and PLL are shut down.– All dynamic operation of the device is suspended.– The DC-DC converter remains operational.– The Flash memory is turned off.All registers and memories retain their state.Wakeup from any enabled wakeup source that can occur withoutclocks, or Reset.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 54. Deep Power Down Mode Similar to Power Down mode, but the DC-DC converter is turned off.– This is only useful if 1.8V power is supplied externally.– Device state is lost (but, see RTC and Battery RAM).Wakeup can only be accomplished by a chip reset or an Alarm interruptfrom the RTC.During Deep PD mode, power may be removed from the entire device,except for the RTC.– Restoring power causes a POR.Wakeup requires that external circuitry restores power.– The alarm output of the RTC can signal external circuitry when powershould be restored, or some external means may be used.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 55. Wakeup from Power Down or Sleep Mode External interrupts– (EINT0 through EINT3) and GPIO interruptsEthernet wakeup– (portions of the Ethernet block receive clocks from the external PHY)USB or CAN activity (pin state change)Brown Out DetectRTC Alarm CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 56. Wakeup from Power Down or Sleep Mode External interrupts– (EINT0 through EINT3) and GPIO interruptsEthernet wakeup– (portions of the Ethernet block receive clocks from the external PHY)USB or CAN activity (pin state change)Brown Out DetectRTC Alarm CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 57. RTC & Battery RAM APBRTC Power DomainVbat 2 KB Battery RAM X1RTC Real Time ClockX2OscillatorAlarmCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 58. NicheLite for LPC by InternicheNicheLite for LPC is a fully featured TCP/IP stack– Requires as little as 12 KB of code. Support for the following protocols:• Address Resolution Protocol (ARP), Internet Protocol (IP), Internet Control Message Protocol(ICMP), User Datagram Protocol (UDP), Transmission Control Protocol (TCP), Dynamic HostConfiguration Protocol (DHCP) Client, Domain Name System (DNS) Client, Bootstrap Protocol(BOOTP), Trivial File Transfer Protocol (TFTP) Includes NicheTask ™ a cooperative multi-tasking scheduler.Supports InterNiche's Light Weight API and a Zero-Copy option.Single Ethernet interface with device drivers optimized for the LPC2300 and LPC2400Example applications (TFTP Client, TFTP Server, HTTP Listener)Source code is free to NXP customersLicense - Unlimited use with NXP LPC2000 and LPC3000 microcontrollers onlySupport from Interniche at sales@interniche.com 58CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 59. LPC24xx LPC24xx features beyond those offered in the LPC23xx. ·More RAM ·Ethernet MII interface (in addition to RMII) ·USB Host and OTG functionality ·External Memory Interface with additional External Memory Controller circuitry ·Additional GPIO ·Additional PWM 59 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 60. LPC24xx Announcement on the webDatasheets by email (LogicPG@NXP.com)2 Devices: – LPC2458: 512KB flash, 98KB SRAM, Ext bus (16-bit), TFBGA180 – LPC2468: 512KB flash, 98KB SRAM, Ext bus (32-bit), LQFP208 & TFBGA208Will be available in Q1 2007LPC24xx LeafletCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 61. LPC3000 Family 32-bit ARM9 Products
  • 62. NXP Standard MicrocontrollerThe Next Generation ….. LPC3000CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 63. Block Diagram LPC3180 External90nm ProcessMemory Interfaces208 MHz Core freq.CPU subsystemNAND Flash ETBI-Cache D-Cache VFP91.2V core operationOn-Chip32kB 32kB Mem ETM9Memory Stick3.3V I/O SDROMARM926EJCard32KB I- & D- caches64 KB DRAMInstr Data SRAMcontrol64KB TCM SRAM(Tightly-Coupled Memory) Up to 1MB SRAM Bus matrix (Multi-layer AHB)(On-Chip Memory) Standard E-ICE InterruptDMAJTAG Interface TimersUART Controller Controller 1-5,7 I2C A Watchdog6KB ETB UART6SysCtrl IrDA(Embedded Trace Buffer) Keyscan I2C B PLLsGPIO256-pin TFBGA package A/D PWMPowerUSBRTCcontrolOTGSPI Other Communication System Functions Peripherals Peripherals CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 64. Technology Announcement First ARM9 family-based microcontrollers in 90nm technology Press release done on Feb 23th during the Embedded World Show Nuremberg: LPC3000 Family based on 90nm technology industry’s first 90nm ARM9* family- based 32-bit microcontroller family. Based on NXP Nexperia platform using the ARM926EJ-S* coreFeatures: Several power management benefits Peripherals such as integrated USB On-the-Go (OTG) and full USB Open Host Controller Interface (OHCI) host Multi-level NAND Flash interface Operating speed at 200MHz Standard communication peripherals like up to 7 UARTs, SPI, I2C, USB, real-time clock, Ethernet - to follow. Floating point Vector Coprocessor 100mW power consumption @200Mhz with all peripherals switched onCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 65. Nohau’s LPC3000 Evaluation BoardA Single power supply input (5.0V), regulated on board ► to provide all the necessary EVB voltages. ►User Reset pushbutton switch. ►20 Way JTAG/ETB connector. ►32M (8M x 32) Bytes of SDRAM. ►32M (32M x 8) Bytes of NAND FLASH. ►1 - LCD Module with Philips PCF8558 built in. ►1 - SD Card connector. ►3 - USB connectors (USB A Receptacle Connector for USB Host; USB B Receptacle Connector for USB Device; USB Mini AB Receptacle Connector for USB OTG) with Philips ISP1301. ►3 - UART (RS232) physical interface circuits connected to standard PC style DB9 female connectors. ►4 - User input pushbutton switches. ►2 - User output LEDs. http://www.nohau.com/emularm/lpc3000_board.htmlCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 66. phyCORE®-ARM9/LPC3180 ARM9 with Vector Floating Point UnitTechnical FeaturesCarrier Board in EURO-card dimensions (100 x 160 mm)RS-232: 2x female DB-9 connectors support UART5 and UART2USB (Host/Device/OTG) connectors:Standard A type connector for USB host functionality, Standard B type connector for USB device functionalityminiAB type connector for OTG functionalityJTAG – 2.54mm pitch, 16-pin connector for JTAG debugging interfaceSD Card slotReset push button, Boot jumper ,2x user buttons4x user LEDs with jumpers to separate from I/O linesBattery receptacle for LPC3180 Real-Time Clock and SRAM back-up Single Board Computer ModuleKeyboard – 2x8 2.54mm pitch connector for keyboard interface1x potentiometer connected to one A/D input PART #: PCM-0315V. low-voltage socket for power supply connectivity3V. and 5V. low voltage supplies for external devices and subassembliesExpansion Bus: address, data, interface and all applicable I/O signals route from implemented phyCOREmodule to 2x80-pin Molex connectors, enabling connectivity to Add-On hardwareMemory configuration:–SDRAM: 16 to 64 MB synchronous SDRAM, max. access time of 10ns, 32-bit organization–Flash: 16 to 128 MB NAND-Flash in 8-bit mode–Serial: 1 to 32 KB I²C-EEPROMPART #: PCM-031 –Configuration:Carrier Board208 MHz, 32 MB SDRAM,32 MB Flash, 32 KB EEPROM, USB OTG, JTAG interface –$249.00 Module only –$349.00 basic package : Module + Carrier BoardPART #: KPCM-976http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-ARM9LPC3180-Kits.html CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 67. Tools and support 16/32-bit ARM7TDMI-S Products
  • 68. Development Tool Support EmbeddedICE-RT™ (JTAG) Embedded Trace Macrocell (ETM) Real Time Monitor with Debug InterruptTrace PortTrace Port10Analyser AnalyserETM: EmbeddedTrace Macrocell6 (JTAG)JTAGARM7-SE-ICE JTAGwith RTMInterface InterfaceDebugger Trace ToolsEmulation & Real Time Trace CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 69. Esacademy Flash MagicFree Flashmagic Utility from Esacademy Features: – Program/Erase Flash– Verify– Blank check– Check ID– Fill Buffer– Save HEX file – Fo more info:http://www.esacademy.com/ CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 70. Development tools - LPC2100/LPC2200 IAR/NXP board for LPC210x 2x 9-pin D-type Serial communications ports LED’s can be connected to selected port-pins 3 switches for interrupts, Reset switch Breakout ports for Logic Analyzer connection Price projection $149 with 32k compilerKeil/NXP board for devices with ADCand optional CAN (LPC2129)2x 9-pin D-type Serial for serial co. ports2x 9-pin D-type Serial for CAN8 status LED’sSwitches for interrupt and ResetPotentiometer for ADC demosPrice projection $149 with 16k compiler(no time limit)CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 71. Ashling ASK-2000 for LPC210x, LPC211x, LPC212x, LPC22xx •LPC2104, LPC2105, LPC2106, LPC2114, LPC2119, LPC2124, LPC2129, LPC2210, LPC2212, LPC2214, LPC2290, LPC2292 and LPC2294, LPC213x •Jtag connector available •Price: $295 with LPC2106 •Add $90 for LPC2129 or LPC2294 •Adapter available for the other 21xx and 22xx derivatives •Emulator integrated in the same board ! http://www.ashling.com/support/lpc2000/eval_kits.html CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 72. Keil MCB2130 Evaluation Board LPC21382x 9-pin D-type Serial for serial communications ports 8 status LED’s Speaker on DAC output Buttons for interrupts and Reset Potentiometer for ADC demos Plated-through-hole prototyping matrix Price: $149 with 16K compiler (no time limit)CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 73. IAR KS2103 Evaluation Board •LPC2103 Development board•LPC2103 MCU • Two serial ports • Reset button • In-system programming (ISP) button • Three user-defined buttons • 16 fully configurable LEDs • 16 character x 2 row LCD screen • Power-on LED • Can be powered via IAR J-Link-KS or external 9-12V DC power supply (not included) • Lithium back-up battery holder • 20-pin JTAG interface connector • Breakout headers for all pins (suitable for mounting daughter boards) • 20x20 array of plated holes for prototyping CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 74. Keil MCB214x Evaluation BoardLPC2148 microcontroller 2x 9-pin D-type Serial for serial communications ports, power amplifier and on board loudspeaker 8 status LED’s Speaker on DAC output Potentiometer for ADC demos SD Card Interface Software support for USB USB Soft Connect feature NOT supportedPrice $149.00 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 75. IAR KS214x Evaluation BoardLCD interface RS232 ports for UART’s Push buttons for external interrupts USB Soft Connect feature supported SD card interface for USB Price $149.00CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 76. PHYTEC phyCORE®ARM7/LPC229x phyCORE-ARM7/LPC229xPCM-023-SK-229410/60 MHz,1 MB SRAM, 2 MB Flash,2 KB EEPROM,SMSC LAN91C111 10/100 Mbit/sEthernet,JTAG interface $199.00http://www.phytec.com/sbc/32bit/pclpc229x.htmCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 77. MCB23xx Keil for LPC2300 familyEvaluation boards from Keil: – MCB2360 (LPC2364/66/68)– MCB2370 (LPC2378) SchematicCode sample on the webPrice: 199$Two serial interfaces,a speaker, analog input (via potentiometer),two CAN interfaces,LCD, SD card interfaceUSB, Ethernet,and eight LEDs make this board a great starting point for your next ARM project.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 78. IAR Kick Start Development Kitfor LPC2378 Contains: • LPC2378 development board • IAR J-LINK-KS JTAG debugger with USB connector • IAR Embedded Workbench with a 32KB version of the IAR C/C++ Compiler • IAR PowerPac: 3 tasks (RTOS) and 1 file (Flash File System) evaluation version • 20-state version of visualSTATEry uabrefFdonee hat t le b aila AvCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 79. Nohau’s LPC2800 evaluation board SD card Connector ►USB connector ► LCD Module ► 16MB SDRAM, 8MB Flash ► Headphone jack ► Price on Nohau’s web site: 995$ ► http://www.nohau.com/emularm/lpc2800.htmlCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 80. ARM Emulators
  • 81. JTAG emulatorsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 82. Emulator with Trace http://www.ashling.com/datasheets/armtools.htmlJlink + Trace CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 83. Debuggers Pathfinder debugger for the LP2100 http://www.ashling.com/datasheets/armtools.htmlARM RealView debugger http://www.arm.com/devtools/ads?OpenDocum ent&View=defaultBody2.Seehau debugger ARM http://www.nohau.com/downloads.htmlC-SPY debugger ARM CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 84. DebuggersChameleon Debugger http://signum.com/Signum.htm?p=ARM.htm Keil debugger & simulator µVision3 http://www.keil.com/arm Universal Debug Engine (UDE)MULTI Debugger CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 85. Integrated Development Environment AsIDERealViewEWARMµVision3 CrossWorks Multi 2000CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 86. CompilersARM Compiler http://www.arm.com/devtools/soft_dev_tools? OpenDocument. GHS Compiler http://www.ghs.com/products/arm_development.html IAR Compiler http://www.iar.com/Products/?name=EWARM GNU GCCCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 87. ARM RTOS
  • 88. RTOS Listing and Ported to … Nucleus Nucleus Tools, Keilboard CMX ARM,KeilKeil ARTX KeilµCOS-IIIAR,Nohau,Keil (appnotesavailable online)FreeRTOS http://www.freertos.org/ CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 89. RTOS ListingeCosAshling NicheTaskThreadX IAR,ARMPumpkin Salvo Keil µClinux See www.uclinux.org CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 90. RTOS SupportNucleus from Accelerated Technology a Mentor companyChronOS™from InterNicheCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 91. ARM Doc and software examples
  • 92. Free link and tools: Free GNU C compiler for ARM7 + related manuals – http://www.gnuarm.com/ Free LPC210x software for flash programming at: – http://www.lpc2100.com/ http://www.lpc2000.com/ Link to the ARM processor core documentation directly from ARM site at:– http://www.arm.com/documentation/ARMProcessor_Cores/index.html NXP ARM selection tools page: – http://www.nxp.com/products/microcontrollers/support/development_tools/tools_by_type/ Yahoo support groups – http://groups.yahoo.com/group/lpc900_users – http://groups.yahoo.com/group/lpc2000/Free online Introduction to ARM – http://www.techonline.com/community/ed_resource/course/14612/ Free LPC2000 Insider's Guide To The NXP ARM7-Based Microcontrollers – http://www.hitex.co.uk/arm/index.htmlCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 93. LPC21xx Driver Support (for free) Keil (using uVusion + Keil compiler) – USB mem: a Standard Memory Mass Storage driver example USB audio: an Audio Device driver example – USB HID: a Human Interface Device class driver example NXP – Virtual COM port: Maps a virtual COM port communication in a USB pipe (see LPC2000 news group, file section) – MMC driver: MMC memory card driver, application note (see NXP web site, microcontroller section) IAR: –USB mouse class driver example –USB MassStorage: Manage a MMC card and a vurtual RAM disk via USB –USB Audio: manage an input and an output audio stream via USB –USB CDC: USB communication device class via virtual COMCDC = Class Definition for Communication Devices Rowley : – TCP/IP, uIP stack for the Olimex LPC-E2124 board @ http://www.rowley.co.uk Free lib: EFSL http://efsl.de (FAT12/16/32 file system with short file names) Keil and IAR examples don’t require any Windows USB class driver. Windows XP supports all mentioned class drivers. NXP supplies the Virtual COM driver for Windows XP, IAR supplies the .inf file for the CDC windows driver CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 94. COMMERCIAL FILE SYSTEM SUPPORT• HCC – Supports fat 16/32 – Wear levelling – About 2000 Eur • Keil – Supports Fat 16 – 8.3 file naming – Part of RTL IAR – Power PACKCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 95. USB Masss-storage class drv. and Filesystem relationshipVirtual DriveCustomer Application Init_USB()Open_File()Read_File() Write_File() Defines device, Windows FAT16/32File system API interfaces,Filesystem APIsendpointsFile system manager USB Mass storage USB Mass storage class driver class driverWrite_mem_blk()SD, MMC init Read_mem_blk() USB device low-levelWindow low-levelmessages driverHOST driver Low Level Memory card driverEx.: USB Device USB HOST EFSL, HCC, IAR power Pack SD/MMC cards Keil RTX FS CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 96. USB booksUSB Design By Example A pratical Guide to Building I/O devices John Hyde, Intel University Press USB complete third edition Jan Axelson, www.Lvr.com Lakeview ResearchCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 97. ARM-Tools on the NXP website http://www.semiconductors.NXP.com/products/microcontrollers/support/development_too ls/tools_by_family/ CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 98. LPC2000 forum Started by Leon Heller, an engineering consultant from England: “The NXP LPC2100 family of ARM MCUs is sufficiently different from other ARM variants that I decided that a forum dedicated to it would be useful.” Direct URL http://groups.yahoo.com/group/lpc2000/ Founded Nov 17, 2003 Already about 4000 members!CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 99. Get the latest Information ....... Product Selection GuideDatasheetsProduction StatusToolsApplication NotesAnd much more …http://www.standardics.nxp.com/ products/microcontrollers/CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 100. Insider’s Guide to LPC2000200 page guide to LPC2000 featuring chapters on: – ARM7 Core– Software Development– System Peripherals– User Peripherals– Keil Tutorial– GNU Tutorial Perfect for engineers without ARM experiencehttp://www.hitex.co.uk/arm/lpc2000book/book_downloadform.html CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 101. Application examples CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 102. http://www.jandspromotions.com/philips2005/ CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 103. NXP ARM Design ContestFlash card … NoPC TAM-TAMMagnetometerNuclear Weighing LAURINCharlie Measurement Ethernet AcquisitionTV-Oscilloscope Dual-Axis Level BuckymeterDuux BabycallSensorDistinctive Excellence CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 104. LPC2000 – Key Points Why ARM?– ARM7 is an open architecture– Already the preferred 32-bit solution in Automotive, Communication and Industrialmarkets.– Same tools for all ARM7 of different manufacturer. Often the same tools can beused for ARM9/10/11. Customers can save money– ARM is a scalable and uniform architecture. ARM7 is binary code compatible withARM9/10. Your customer can chose the right product for its target applicationsaving time due to the reduced learning curveWhy NXP?– First ARM7TDMI supplier with on-board flash in 0.18 μm process, with the largestARM7 product portfolio– Memory sizes from 8k up to 1M on-chip flash– Highest flash performance with nearly zero wait states due to internal MAM (MemoryAccelerator Module)– Widest selection of devices and of the integrated peripherals: 4*CAN, 2*ADC, SPI,I2C…)– Lowest pin count and smallest packages available– Price level allows to address mid/high end 16-bit applications, and high end 8 bitapplication CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 105. Hands-OnCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 106. Hands-OnHands-On Index Tools Setup 1. Oscillator / PLL / MAM / GP I/O / Flash 2. ADC 3. Interrupts / Timer 4. UART / CAN 5. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 107. Hands-On Start Keil uVision3Menu Selection: Project / Compile Current File Open Project Select Make Project Blinky1 Rebuild Project (all) Open Options Dialog Start/Stop DebuggingCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 108. Hands-On Build and Debug Build Project ResetRun HaltStart Debugging Step into Step overPerformance AnalyzerSignal Analyzer CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 109. Hands-On Setup of Logic Analyzer Add NewLogic Analyzer signal – Setup – Add signal “action” Here: 10CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 110. Hands-On Run Program View Variables and RegistersMenu:Peripherals /GPIO /Port1 Zoom:In & Out CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 111. Hands-On Run Program on Hardware Halt Using JTAG/ULINK– Select Debug Tab– UseStop Debugging“ULINK ARM Debugger” With Flash ISP UtilityOptions– Select Utilities Tab– Use External Tool– Modify Command LineMake Settings:– Run IndependentPress Load ButtonCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 112. Introduction to the ARM architecture
  • 113. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 114. ARM Holdings plc. (1)Established as Advanced RISC Machines Ltd. in 1990 as a UK based joint venture between Apple Computer, Acorn Computer Group and VLSI Technology*– Apple and VLSI provided funding– Acorn supplied technology and first 12 engineersIntroduction of ARM6™ family in 1991, VLSI initial licensee In April 1998 listed on the London Stock Exchange and Nasdaq *: part of Philips since 1999 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 115. ARM Holdings plc. (2)Develops the ARM range of RISC processor cores Licenses its RISC microprocessor core and SoC IP to a network of partners; semiconductor and system companies ARM does not manufacture silicon itself Also licenses architectural extensions, development tools, peripheral IP and SoC solutions ARM’s market share of the embedded RISC microprocessor market is approx. 75% and to date, ARM Partners have shipped more than one billion ARM core- based microprocessorsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 116. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8.CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 117. Bus Width ARM7 is a 32-bit architecture– Data pathes and (ARM) Address Businstructions are 32 bits wideIncr.Address Register – Von Neumann architecture Instruction Decode &• instructions and data use the GeneralRegisters Controlsame 32-bit data busMult.Thumb– There is a subset of 16-bit Decom-pression Shifter instructions (Thumb) optimizedfor code density* ALU Data Out Data In Data Bus *: from C code CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 118. Thumb StateSet of instructions re-coded into 16 bits– Improved code density by ~ 30%– saving program memory spaceIn Thumb state only the program code is 16-bit wide– after fetching the 16-bit instructions from memory,they are de-compressed to 32 bit instructions beforethey are decoded and executed– all operations are still 32-bit operations CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 119. Data Types and Alignment Definitions (Little endian or big endiand are options):– Word =32 bits (four bytes)– Halfword =16 bits (two bytes)– Byte =8 bits 12 34123 4Word Word Halfword HalfwordHalfwordHalfword ByteByte ByteByteByte Byte ByteByte Halfword HalfwordWordWordCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 120. Processor ModesARM has seven operating modes 1. Userunprivileged mode under which most applications run 2. FIQ entered, when a high priority (fast) interrupt is raised 3. IRQ general purpose interrupt handling 4. Supervisor protected mode for the operating systementered on reset or software interrupt instruction5. Systemprivileged mode using the same registers as user mode(not in ARM architectures 1, 2 and 3)6. Abort used to handle memory access violations 7. Undefined used to handle undefined instructionsCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 121. Registers (1)An ARM core has 37 registers (32-bits wide)General purpose registers– 1 program counter– 30 general purpose registers Status registers– 1 current program status register– 5 saved program status registers These registers are not all accessible at the same time. The processorstate and operating mode determine which registers are available to theprogrammer. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 122. Registers (II)Depending on processor mode one of several banks is accessible. Each mode can access– the program counter r15 (PC)– a particular r13 (stack pointer SP)– a particular r14 (subroutine link register, LR)– a set of r0-r7 registers, and a particular set of r8-r12– the current program status register (CPSR)Privileged modes (except Sytem mode) can also access– a particular SPSR (saved program status register)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 123. Register OverviewUser and SystemFIQIRQ Supervisor Abort Undefined r0r0r0r0 r0r0 r1r1r1r1 r1r1 r2r2r2r2 r2r2 Thumb stae Lowr3r3r3r3 r3r3 r4r4r4r4 r4r4 registers r5r5r5r5 r5r5 r6r6r6r6 r6r6 r7r7r7r7 r7r7 r8r8 r8_fiq r8 r8r8 r9_fiqr9 r9 r9r9r9r10_fiqr10r10 r10 r10 r10 Thumb stae Highr11_fiqr11r11 r11 r11 r11r12_fiqr12r12 r12 r12 r12r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP) r13 (SP) registersr14_fiq (LR) r14_irq (LR) r14_svc (LR) r14_abt (LR) r14_und (LR) r14 (LR) r15 (PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC)r15 (PC) CPSRCPSR CPSRCPSR CPSRCPSR SPSR_svc SPSR_fiq SPSR_irqSPSR_abtSPSR_undCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 124. Registers in Thumb State The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:– eight general registersr0 - r7– the program counterPC– a Stack pointerSP– a Link registerLR– the current program status register CPSR In Thumb state, the high registers (r8 - r15) are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storageCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 125. Thumb vs. ARM r0 r0 r1 r1 r2 r2 Thumb state r3 r3 r4 r4 Low registers r5 r5 r6 r6 r7 r7r8ThumbARMr9StateState r10 Thumb state r11High registersr12r13 (SP) r13 (SP)r14 (LR) r14 (LR)r15 (PC) r15 (PC)CPSRCPSR SPSRSPSRCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 126. Program Status Register (1)31 30 29 28 2724 2316 15 8 76540 mode NZ C V QJIFTControl bits Condition Reserved code flagsCondition Code Flags – N: Negative or less than – Z: Zero – C: Carry or borrow or result of the shift operations – V: Overflow To not disturb reserved bits, a read-modify-write strategy should be applied to change PSR bits.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 127. Program Status Register (2) 31 30 29 28 2724 2316 15 8 76540 mode NZ C V QJIFTControl bits Condition Reserved code flags Mode Bits Interrupt Disable Bits – I: IRQ interrupts disable10000 User – F: FIQ interrupts disable10001 FIQ10010 IRQ T Bit10011 Supervisor – Thumb mode (when set)10111 Abort – ARM mode (when cleared)11011 Undefined11111 SystemCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 128. Program Counter (r15) When the processor is executing in ARM state– all instructions are 32 bits wide– all instructions must be word aligned– bits [31:2] contain the PC, bits [1:0] are zero(instructions cannot be halfword or byte aligned)When the processor is executing in Thumb state– all instructions are 16 bits wide– all instructions must be halfword aligned– bits [31:1] contain the PC, bit [0] is zero(instructions cannot be byte aligned) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 129. Exception Exceptions result whenever the normal flow of aprogram has to be halted temporarily, for exampleto service an interrupt from a peripheral. Beforeattempting to handle an exception, theARM7TDMI-S preserves the current processorstate so that the original program can resumewhen the handler routine has finished. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 130. Exception Handling Entering an exception the ARM core– saves the address of the next instruction in the appropriate LR PC + 4 or PC + 8r14_<mode> (LR)r15 (PC)– copies the CPSR into the appropriate SPSR SPSR_<mode> CPSR– sets appropriate CPSR bits• interrupt disable bits 87 65 4 0mode CPSR:I FT• mode field bits• if running in Thumb state, enter ARM state*Control bits – forces PC to fetch next instruction from relevant exception vector *: all exceptions are handled in ARM state!CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 131. Exception Vectors Vector Table... FIQ0x1C IRQ0x18(Reserved)0x14Data Abort0x10Prefetch Abort0x0CSoftware Interrupt0x08 Undefined Instruction0x04Reset0x00 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 132. Multiple ExceptionsException priorities– When multiple exceptions arise at the same time, a fixed prioritysytem determines the order in which they are handled 1. Reset highest priority 2. Data Abort (data memory access cannot be completed) 3. FIQ 4. IRQ 5. Prefetch Abort (instruction memory access cannot be completed) 6. Undefined Instruction 7. SWI - Software Interruptlowest priority (to enter supervisor mode)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 133. Leaving ExceptionTo leave an exception, the exception handler must– copy SPSR back into CPSRSPSR_<mode>CPSR(automatically restoring also I, F and T)8 76540modeCPSR: IFTControl bits– move contents of current LR minus offset* to PC PC - offset r14_<mode> (LR) r15 (PC)– *: varies according to type of exception: 2, 4 or 8 CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 134. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 135. Instruction Set All instructions are 32-bits long Many instructions execute in a single cycle Instructions are conditionally executed ARM is a load / store architecture– via registers => RISCLoad or store multiple registers in a single instructionusing <register list>CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 136. Conditional Execution MnemonicDescriptionEQEqualNENot equalCS / HS Carry Set / Unsigned higher or sameCC / LO Carry Clear / Unsigned lowerMINegativePLPositive or zeroVSOverflowVCNo overflowHIUnsigned higherLSUnsigned lower or sameGESigned greater than or equalLTSigned less thanGTSigned greater thanLESigned less than or equalALAlways (normally omitted) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 137. Instruction Examples Data processing instructions– SUBr0, r1, #5r0 := R1 - 5 – ADDr2, r3, r3, LSL #2r2 := r3 + (r3, LSL #2) – ADDS r4, r4, #0x20 r4 := r4 + 32 and set flags– ADDEQ r5, r5, r6 r5 := r5 + r6 if equalSpecific memory access instructions– LDRr0, [r1, #4]r0 := [r1 +4] – STRNEB r2, [r3, r4][r3 + r4] := r2 Byte operation if Z = 0; ignores r2[31:8]– LDRSHr5, [r6, #2]! r5 := [r6 + 2] Halfword sign-ext. set bit [31:16] to bit 15 then r6 := r6 + 2CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 138. Thumb Instruction Subset Subset of most commonly used 32-bit ARM instructions– 2 address format: destination register same as one source registersCompressed into 16-bit wide code– Improved code densityDecompressed on execution to full 32-bit instructions– transparently– in real-time– no performance lossARM code can be combined with Thumb code for maximum flexibility CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 139. Thumb Instructions ARM instruction setThumb instruction set 15 0 31 0RecodingThumb instruction ARM instructionThumb instruction ARM instructionThumb instruction ARM instructionThumb instruction ARM instructionThumb instruction ARM instructionThumb instruction ARM instructionThumb instruction ARM instructionCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 140. Thumb Instruction Set (1)Instruction Types– Branch • Unconditional± 2KBytes • Conditional± 256Bytes • Branch with Link ± 4MBytes (2 Instructions!)• Branch and exchangechange to ARM state if Rm[0] = 0• Branch and exchange with Link– Data Processing • Subset of ARM data processing instructions • Not conditionally executed (but some update flags) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 141. Thumb Instruction Set (2)Instruction Types– Load and Store • Register plus 5-bit (PC,SP plus 8) immediate addressing • Register plus Register addressing– Load and Store Multiple • Load / Store list of registers • Push / Pop(ARM equivalent: STMDB SP!, <registers>)– Exception Generating Instructions • SWI (switch to ARM mode and privileged mode) • Breakpoint(prefetch abort, with debug monitor) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 142. Translation of Thumb Instruction Example: ADD Rd, Rd, # Constant Thumb code150001 10 Rd8-bit immediateMajor op-codeMinor op-codedenoting format 3Immediate Destination anddenoting ADDmove/compare/add/sub/value source registerinstructionwith immediate value 3101110 001 0100 1 0 Rd 0 Rd0000 8-bit immediateARM code Always condition code CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 143. ARM and Thumb Interworking Switch between ARM state and Thumb state using BX instruction– In ARM state: BX<condition> Rn– In Thumb state: BX Rn 31 1 0Rnn: 0-15ARM / Thumb selection BX 0:ARM state 1:Thumb state31 1 0Destination 0addressCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 144. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 145. ARM7TDMI-SThe ARM7TDMI-S is based on ARM7 core – 3 stage pipeline – Von Neumann architecture – CPI ~1.9 – T: Thumb instruction set – D: includes debug extensions – M: enhanced multiplier (32x8) with instructions for 64-bit results – I: core has EmbeddedICE logic extensions – S: fully synthesisable (soft IP) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 146. ARM7TDMI-S CoreAddress BusIncr.Address Register InstructionDecode &RegistersGeneralControl Mult. Thumb Decom- Shifter pression ALU Data OutData InData Bus CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 147. 3-Stage Instruction PipelineARMThumb Instruction Fetched from Memory PC PCFetchThumb only: Thumb instruction Decode PC - 4 PC - 2 decompressed to ARM instruction Instruction decoded Registers read from Register Bank, Execute PC - 8 PC - 4 Shift and ALU operations performed, Registers written back to Register BankCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 148. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 149. Example ARM based SystemARM core RAM 16 bit wide I/O InterruptPeripherals Controller ROMRAM 8 bit wide32 bit wideCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 150. AMBA Advanced Microcontroller Bus Architecture– on-chip interconnect– established, open specification– framework for SoC designs– enabler for IP reuse– ‘digital glue’ that binds IP cores togetherCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 151. Example AMBA SystemARM core Keypad UARTHigh- bandwidthAPBAPBAHBTimer MemoryBridgeInterfaceDisplay RTCDMA High-bandwidthBus Masteron-chip RAM I/O CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 152. AHB and APB / VPB Advanced High-Performance Bus– high-performance– pipelined– fully-synchronous backplane– multiple bus mastersAdvanced Peripheral Bus/ VLSI Peripheral Bus– low-power– non-pipelined– simple interface– wait support(VPB) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 153. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. Q&A 8. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 154. Pipeline-Changes for ARM9TDMI ARM7TDMIFetch Decode ExecuteARM decodeThumb→ARMReg. Reg. Instruction FetchShift ALU decompressread write Reg. select CPI:∼1.9ARM9TDMIFetchDecodeExecute MemoryWritebackARM or Thumbinstruction decode MemoryReg. Shift + ALUInstruction accesswrite Reg. Reg. Fetchdecoderead CPI:∼1.5CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 155. Development of the ARM ArchitectureImproved Jazelle4 Halfword and ARM/ThumbsignedInterworking1halfword / 5TCLZ SA-110Java byte support Instruction5TEJ bytecode Systemexecution SA-11102 modeSaturated maths5TEARM9EJ-S DSP multiply- Thumbaccumulate4T3instruction setinstructionsARM7EJ-SARM7TDMIARM9TDMI ARM1020E ARM9E-SEarly ARM ARM926EJ architectures -S ARM940T ARM966E-ARM720TX-ScaleS T: Thumb E: DSP-extensions S: synthesizableJ: Java:ISA (Instruction Set Architecture): Core Architecture CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 156. ARM Technology Roadmap 0.12µ 0.15µ 0.15µ 0.18µ 400 Performance MIPS (Dhry 2.1) ARM 11 (ARM 10)0.25µ 0.25µ0.18mm 2.4mm2 0.35µ 70-150 DSP MIPSARM 9E 4.8mm2 ARM 9... 100 Harvard 5 Stage Pipeline 0.18µ Von Neumann 0.25µ< 0.5mm2 3 Stage Pipeline 1.0mm20.35µ2.1mm2 0.6µ4.8mm2 ARM 7 Thumb Family 199719981999 2000 2001 20021996CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 157. ARM - The Company 1. Architecture 2. Instruction Set 3. ARM7TDMI-S 4. Systems 5. Other ARM cores 6. NXP Implementation 7. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 158. LPC2xxx minimum peripherals set Some common features– ARM7TDMI-S core with E-ICE RTM™ / ETM™– Operation up to 60MHz– 32-bit timers•2(4 capture and 4 compare channels each)• PWM (6 outputs)• RTC• Watchdog– 2 UARTs (16C550)– I²C (400kb/s) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 159. NXP ImplementationMemory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block 4. Vectored Interrupt Controller 5. Integrated Peripherals 6. Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC,Watchdog, ADC, USB, CAN, Ethernet, SD, IIS, GPDMACONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 160. LPC2000 Memory Map4.0 GB 0xFFFF FFFF AHB Peripherals 0xF000 0000 3.75 GB 0xEFFF FFFF VPB Peripherals 0xE000 00003.5 GB Memory blocks not drawn to scale!Reserved for External Memory3.0 GB 0x8000 0000 2.0 GB Boot Block (re-mapped from On-Chip Flash) 0x7FFF E0000x7FE0 0000 8 KB On-Chip Static RAM, USBRAM on AHB 0x7FD0 0000 16 KB On-Chip Static RAM, ETHERNET Reserved for On-Chip MemoryRAM on local bus 0x4000 nnnn* 16 / 32 / 64 KB On-Chip Static RAM 0x4000 0000 -> fast access ! 0x3FFF FFFF1.0 GBReserved for On-Chip Memory 0x000m FFFF 8KM ... 1MB On-Chip Non-Volatile Memory0.0 GB 0x0000 0000CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 161. Flash Memory Organization • The boot block alwaysLPC213X resides in the top of Flash512k 0x07 FFFF 12K Boot Block and contains the boot loader0x07 CFFF Sector 264K •Active interrupt vectors could Active Exception Vectors… Sector 224k be from Flash, SRAM or boot 0x3F block. On reset the boot block0x00 Sector 21 32K vectors are always mapped to… 0x0 Sector 15 32kLPC2100, 256k256k 0x03 FFFF 8K Boot Block Sector 14 32K0x03 FFFF …Sector 16 8K LPC2100, 128k Sector 11 32k …128kSector 10 8k0x01 FFFF0x01 FFFF 8K Boot Block Sector 10 32K Sector 9 64KSector 14 8K Sector 9 32KSector 13 8K Sector 8 64K64k 0x00 FFFF Sector 8 32KSector 12 8KSector 7 8K32k 0x00 7FFF … … Sector 7 4KSector 2 8k Sector 2 8k ... Sector 1 4KSector 1 8K Sector 1 8K Sector 0 4KSector 0 8K Sector 0 8K0x0 0x00x0CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 162. SRAM: 8, 16, 32 or 64 KB0x4000FFFF 64KB SRAM0x40007FFF32KB SRAM0x40003FFF 8KB SRAM 16KB SRAM0x40001FFF0x4000003FRAM Int VectRAM Int Vect RAM Int VectRAM Int Vect0x40000000CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 163. Memory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block 4. Vectored Interrupt Controller 5. Integrated Peripherals 6. Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC,Watchdog, Ethernet, SD, IIS, GPDMA CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 164. System ControlIncludes a number of important system features– Power Control– Memory mapping configuration– Oscillator– PLL– VPB (VLSI Pheriperal Bus) divider– Reset (active low)– Wakeup Timer– External InterruptsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 165. Power Control 1 • Power Control Register[PCON – 0xE01FC0C0] R/W PCON[0] IDLIdle mode - processor clockstopped, on-chip peripherals remainactive, interrupts cause wakeup PCON[1] PD Power Down mode - oscillator andon-chip clocks stopped, wakeup byexternal interruptFor example 5 mA with most20 uA at roomperipherals powered down temperature, 50 uA with single Biggest factors:voltage supply temperature, clock rates Peripheral Clock Divider: 20%CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 166. Power Control 2 • When disabled, peripherals are switched off to conserve power • Power Control for[PCONP – 0xE01FC0C4]R/W Peripherals RegisterPCONP 1 PCTIM0Enable Timer0 PCONP 2 PCTIM1Enable Timer1 PCONP 3 PCURT0Enable UART0Each peripheral PCONP 4 PCURT1Enable UART1typically below 1mA PCONP 5 PCPWM0 Enable PWM0 PCONP 7 PCI2C Enable I2C PCONP 8 PCSPI Enable SPI PCONP 9 PCRTC Enable RTC ......CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 167. Power Control (3) • Power Control for Peripherals Register cont'd ...PCONP 8 PCSP0 Enable SPI0PCONP 9 PCRTC Enable RTCPCONP 10PCSPI1Enable SPI1PCONP 11PCEMC Enable External Memory ControllerPCONP 12PCADEnable A/D-ConverterPCONP 13PCCAN1Enable CAN Controller 1 Acceptance Filter PCONP 14PCCAN2Enable CAN Controller 2 enabled with anyCAN Controller PCONP 15PCCAN3Enable CAN Controller 3PCONP 16PCCAN4Enable CAN Controller 4CAN peripheraltypically below 2mA CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 168. Boot BlockThe uppermost Flash sector contains the Boot Loader– controls physical interface for programming and erasing the Flash– supports ISP (In System Programming) mode for initialprogramming of customer code– supports In-Application Programming in a running system underthe control of customer software– buffers an entire Flash line (512 bytes) at once to keepprogramming time to a minimumThe Boot Loader is automatically run following reset– checks for a “Valid User Program” key to prevent running code onincorrectly programmed devicesCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 169. Flash Memory IAP Programming IAP: In Application ProgrammingBootloader contains flash programming routines – Erase Sectors – Write blocks (of 512 bytes)• Re-write to blocks possible, if bits are cleared in 32 byte groups(see hands-on example) – Common entry point for IAP calls: 0x7ffffff1 During calls, all interrupts must be disabled – Note: hands-on example only disabled IRQ, not FIQCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 170. BOOT PROCESS FLOWCHART LPC23/24 only CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 171. Exception Vectors Vector Table. . .FIQ 0x1C Valid user program key:IRQ 0x18 Must contain a value that (Reserved) 0x14 ensures that the checksum of all vectors is zero Data Abort 0x10 Prefetch Abort 0x0C Software Interrupt 0x08Undefined Instruction 0x04 Reset 0x00CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 172. Memory Mapping Control 1Re-mapping of Exception Vectors– always appear to begin at 0x0000 0000– but can be mapped from different sources: • User Flash – Exception Vectors are not re-mapped and reside in Flash On-chip Flash Memory0x0000 003F Active Exception Vectors0x0000 0000 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 173. Memory Mapping Control (2) • Boot Loader – Always executed after reset. Exception Vectors re-mapped from Boot Block• User RAM – Exception Vectors are re-mapped from RAMOff-chip Memory 0x8000 0000On-chip User RAM 0x4000 0000 Boot Loader On-chip User Flash Memory 0x0000 003F Active Exception Vectors 0x0000 0000CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 174. Memory Mapping Control (3)Re-mapping of Boot Block– mapped from top of Flash to top of on-chip memory space2.0 GB On-chip User RAMBoot Loader On-chip User Flash Memory0x0000 003F Active Exception Vectors0x0000 0000CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 175. Memory Mapping Overview4.0 GB 0xFFFF FFFFAHB Peripherals VPB PeripheralsReserved for External Memory 2.0 GB Exception Vector0x7FFF FFFFBoot Block (re-mapped from On-Chip Flash) re-mappingReserved for On-Chip MemoryBoot Blockre-mapping16/32/64 KB On-Chip Static RAMReserved for On-Chip Memory 8KB Boot BlockActive Exception Vectors128 KB On-Chip Non-Volatile Memory0x3F 0x0000 00000x00CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 176. Memory Mapping Control Register • Memory Mapping Control [MEMMAP – 0xE01FC040] R/W MEMMAP 1:0MAP 1:000: Boot Loader Mode01: User Flash Mode (no re-mapping)10: User RAM Mode11: External MemorySelects the memory being mapped to address zero CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 177. Phase Locked Loop (1)10 to 25 MHz input clock frequency Output frequency from 10 MHz up to the max. CPU rate (LPC2xxx: 60MHz)Programmable frequency multiplication PLL bypassed on reset PLL lock indicator can be used as an interrupt to connect the PLL once it is locked PLL programming requires a special feed sequence (like the watchdog) for safetyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 178. Phase Locked Loop (for old families LPC21xx and LPC22xx)156 to 320 MHz 10 to 60 MHz Fosc * 2 * M * P Fosc * M FOSC FCCO XTAL1cclkCurrent Phase ControlledOscillator ÷ 2PDetector Oscillator Divider Value 10 to 25 MHzVPB pclk 1 to 30 MHz÷M Divider without PLL ÷ 1/2/4 Default: 4P:=1..8 Multiplier ValueM:=1..32 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 179. Phase Locked Loop (3) cclk: processor clock frequency10 ... 60-70MHz Fosc: crystal oscillator or input frequency 10 ... 25MHz Fcco: PLL CCO-frequency156 ... 320 MHzFcco cclk = M • FOSCcclk = 2•PFCCO = cclk • 2 • PFcco= Fosc • M • 2 • P Example: FOSC = 10 MHz (crystal controlled)Target: cclk = 60 MHz60 MHz cclk M= ==610 MHz FoscSelect suitable value for P: FCCO = 60 MHz • 2 • P = 240 MHz(P = 2)CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 180. PLL Registers (1)• PLL Control Register[PLLCON – 0xE01FC080] R/W PLLCON0PLLEPLL Enable PLLCON1PLLCPLL Connect • PLL Configuration Register [PLLCFG – 0xE01FC084]R/W PLLCFG 4:0 MSEL 4:0PLL Multiplier value quot;Mquot; (M-1) PLLCFG 6:5 PSEL 1:0PLL Divider value quot;Pquot;00: 101: 210: 411: 8CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 181. PLL Registers (2)• PLL Feed Register[PLLFEED – 0xE01FC08C]WO PLLFEED 7:0PLLFEEDConsecutive writes 0xAA then 0x55 • PLL Status Register[PLLSTAT – 0xE01FC088]RO PLLSTAT 4:0MSEL 4:0Readback for Multplier value quot;Mquot; (M-1) PLLSTAT 1:0PSEL 1:0Readback for Divider value quot;Pquot; (1,2,4,8) PLLSTAT 8PLLEReadback for PLL Enable bit PLLSTAT 9PLLCReadback for PLL Connect bit *PLLSTAT10PLOCK Reflects PLL Lock status * Cleared when Power Down mode activatedCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 182. VPB Divider Register• VPB Divider Register[VPBDIV – 0xE01FC100]R/W VPBDIV 1:0 VPBDIVcclk / pclk ratio 00: 401: 110: 2 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 183. Memory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block 4.Pin Connect Block / External Memory Controller Vectored Interrupt Controller 5. Integrated Peripherals 6.Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC, Watchdog, ADC, CAN CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 184. On-chip Memory with 0-wait StatesARM7TDMI-S is a 1-clock core– CPI of ~1.9, but many instructions execute in 1 cycle– CPU requires one instruction per clock cycleFor highest performance 32 bits needed with every clock Memory access time < 17ns @ 60MHz CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 185. Memory Accelerator ModuleCPU performance limited by Flash access time (<50 ns)– ARM needs 32 bits every clock for 1 clock instructions– Without MAM operation possible up to 20MHzFlash Architecture– Flash is split into two blocks of 128 bits each• 128 bits are accessed at once– Separate Branch Trail Buffer holds 128 bits of history of each block=> 4-times speed improvement for linear code; branches will cause avariable delay, depending on target address– Additional Data Buffer for data accesses to Flash CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 186. Memory Accelerator Module Address BusARM7Bus Interface CoreFlash MemoryFlash Memory Bank 1Bank 2128 bit 128 bitPrefetch Buffer 1 Prefetch Buffer 2 Local BusBranch Trail Buffer 1 Branch Trail Buffer 2 128 bit (2x)128 bit (2x) Data BufferSelection Data Bus (32 / 16 bit) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 187. MAM Registers• MAM Control Register [MAMCR – 0xE01FC000] R/W MAMCR 1:0 MAM mode 00: MAM functions disabled control01: MAM functions partially enabled *10: MAM functions fully enabled11: reserved* Only sequencial code via MAM • MAM Timing Register[MAMTIM – 0xE01FC004]R/W MAMTIM 2:0MAM Fetch000: reserved Cycle timing001: MAM fetch is 1 clock cycle...111: MAM fetch is 7 clock cyclesCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 188. Hands-OnHands-On Index Tools Setup 1. PLL / MAM / GP I/O / Flash 2. ADC 3. Interrupts / Timer 4. UART / CAN 5.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 189. Hands-On PLL and MAM Setup with Keil uVision, Project Blinky1 The PLL and MAM settings are part of the startup code Settings can be made using a convenient input mask Exercise: Setup the PLL to 60Mhz CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 190. Hands-On MAM Setup Enabling the MAM for60Mhz clock and 50ns Explanation of MAMFlash Register values– “Partially Enable”:Code fetches onlySetup MAM– “Fully enable”:Code and data fetches– MAM Timing“Fully Enable”Number of clock cyclesMAM Timing “3”used for one flash 3 * 17ns = 51nsmemory access CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 191. Hands-On Verify PLL and MAM SettingsOpen disassembly window and single step through while loop in function “wait” Every loop needs 6 cycles:3 instructions at 1 CPI1 instruction (branch) at 3 CPI In Simulation == In Hardware if MAM is full enabled– If the define LOOP_DELAY is 1.000.000– 6.000.000 cycles are realized in the delay()– “action” incremented every 100ms at 60Mhz CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 192. Hands-On Flash IAP Project FlashSWIntLoad and single step – Watch memory at 0x8000, ASCII modeExercise:Change program to use address 0x10200for storing the stringCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 193. Memory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block 4. Vectored Interrupt Controller 5. Integrated Peripherals 6. Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC,Watchdog, ADC, CAN CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 194. General Purpose I/O (1) Pins available for GPIO: LPC21/22– 48-pin devices: 32– 64-pin devices: 46– 144 pin devices:76 (max.) (with external memory)112 (w/o external memory) LPC23/24 – Up to 160 GPIO pins, all implemented as fast GPIOs, with 64 GPIO interrupts (plus 4 other external interrupts). Shared with– Alternate functions of all peripherals– Data/address bus and strobe signals for external memories CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 195. General Purpose I/O (2) Direction control of individual bits Separate set and clear registers Pin value and output register can be read separately Slew rate controlled outputs (10 ns) 5 registers used to control I/OsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 196. General Purpose I/O 2 Register IOPIN The current state of the port pins is read from this register Writing quot;1quot; sets pins high, writing quot;0quot; has no effectIOSETWriting quot;1quot; sets pins low and clears corresponding bits in IOSETIOCLR Port pin direction: 0 = INPUT 1 = OUTPUTIODIR Selects function of pins (Pin Connect Block) PINSEL0/1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 197. Conventional GPIO Implementation Drawbacks Conventional ARM GPIO is implemented on the APBperipheral busToggling speed of the GPIO is limited due to the 3-stagepipeline, AHB bridge and the APB bus CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 198. Understanding the slow port behavior It takes 5 clocks to execute a port writeTotal time from instruction fetch to port change is 7 clocksMaximum achievable period is 14 clocks (cclk/14) = (60/14) = 4.28MHz When cpu_clken_I is low indicates core is stalled CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 199. Block diagram of new port configurationCONFIDENTIAL10Subject/Department, Author, MMMM dd, yyyy
  • 200. Improving Speed GPIO registers are now interfaced directly to theARM7 Local busPorts can now toggle every 2 clocks giving a clockperiod of cclk/4= 15Mhz This is a 3.5x speed increase Enables faster ‘soft’ peripherals CONFIDENTIAL 9 Subject/Department, Author, MMMM dd, yyyy
  • 201. Results of change (speed of writes)Port output FetchingFetchingFetching FetchingFetchingFetching E580500 E580500 E580500Writing Writing Writing DecodingDecodingDecodingDecodingDecodingDecoding E5803000 NothingE5804000 NothingE5805000 Nothing Executing Executing Executing Executing Executing Executing E5802000E5803000E5803000E5804000E5804000E5805000 CONFIDENTIAL 6 Subject/Department, Author, MMMM dd, yyyy
  • 202. Fast GPIO Special features – GPIO registers accessed via ARM local bus in addition to conventional peripheral bus access – Mask registers allow treating sets of port pins as a group, leaving other bits unchanged – Local bus GPIO registers are now byte addressable – Entire port value can be written in one instruction using the IOPIN register CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 203. Mask Register- Advantages Provides the capability to the user to separate the GPIO pins intogroupsAny modifications to the FIOSET,FIOCLR and FIOPIN is only effected ifthe corresponding bits in the FIOMASK are setUsing Mask registers… Individual I/O pins can be addressed separatelyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 204. Pin Connect Block (1)Many on-chip functions can use I/O pins Number of I/O-pins is limited⇒ I/Os can be configured to adapt various functions Configuration done by Pin Connect BlockPINSEL0/1/2 GPIO UARTPIN Timer/Counter reserved CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 205. Pin Connect Block (2) Pin Function Select Registers– PINSEL0 and PINSEL1 • Configuration of P0 • Assign P0.0 ... P0.31 to GPIO or an alternate function (1 of max. 3) – PINSEL2 (not available in 48-pin devices)• Configuration of P1 (64/144-pin devices) and P2, P3 (144-pin devices) • Select availability of debug and trace ports on Port1 pins • Controls use of address/data bus and strobe pins(144-pin devices)• Selection of additional ADC-inputs(144-pin devices)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 206. Pin Connect Block (3) Example:... • Pin Function Select Register 0 [PINSEL0 - 0xE002C000)] R/W .........PINSEL0 21:20P0.1000: GPIO Port 0.10 01: RTS (UART1) 10: Capture 1.0 (Timer 1) 11: reserved.........CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 207. External Memory Controller* (1) Supports static memory devices (RAM, ROM, external I/O)Up to 4 independent banks, each up to 16M BytesProgrammable– Bus turnaround (idle) cycles (1 to 16)– Read and write WAIT states (up to 32)– Write protection– Burst mode operation– External data width: 8, 16, or 32 bits *: LPC2000 144-pin devices only, LPC2378, LPC24xx CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 208. External Memory Controller* (2)Available signals Pin name Type DescriptionD [31:0]Input / Output External memory data lines A [23:0]Output External memory address lines OEOutput Output Enable (active low) BLS [3:0] Output Byte Lane Select (active low) WEOutput Write Enable (active low) CS [3:0]Output Chip Select (active low)*: 144-pin devices only CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 209. External Memory Controller* (3) Selection of external data bus width(144-pin devices only)– Determined by state of pins Boot0 and Boot1 during Reset P2.27 / D27 / Boot1 P2.26 / D26 / Boot0Boot from00 8-bit memory on CS001 16-bit memory on CS010 32-bit memory on CS011Internal Flash memory *: 144-pin devices onlyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 210. External Memory Controller* (4)Size of external memory – Number of external address lines defined byPINSEL2 27:25 – Remaining port pins available as GPIO111 110 101 100 011 010 001 000 decoded to CS0 ... CS3 31 30 29 28 27 26 25 24 23 20 19 16 15 12 11 8 7654 3210*: 144-pin devices onlyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 211. Hands-On GPIO Exercise Optional Exercise:Exercise: “Invent” a display patternModify the example indicating seconds andto use a macro or function 125msfor LEDsExamples:Hint:– Walking LED, or – SET_LEDS(byte)– Bar indicator – LEDs are on Port 1, bits 16-23 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 212. Memory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block / Memory 4.ControllerVectored Interrupt Controller 5. Integrated Peripherals 6. Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC,WatchdogCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 213. Vectored Interrupt Controller ARM PrimeCell™ 32 interrupt request inputs 16/32 IRQ interrupts can be auto-vectored (in the LPC23/24)– single instruction vectoring to ISR– dynamic software priority assignment32 FIQ non-vectored interrupts 32 Software interrupts CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 214. Vectored Interrupt Controller FIQStatus 32 FIQ OFIQFIQTimer Interrupt SourceR FIQ IntEnableClearRawInterrupt 32interruptIntEnableOHigh PrioR VectorCntl SoftIntClear En ChannelVICVectorAddr 0CSoftInt IRQStatus50:4P IRQ...U16/32 (LPC23/24)32En Channel VICVectorAddr 15/31IntSelect50:4VICDefVectAddr Low Prio Known FIXED ADDRESSIRQ VICVectorAddr 0VICVectorAddVICVectAddD[0..31]D[ ] CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 215. IRQ Interrupts VectoredVectoredFIQ Interrupt ARM-CoreInterrupt Controller ControllerIRQ InterruptTimerTimer Channel #4Channel #4 (Overflow)(Overflow)VIC VectorAddressChannel #16Channel #16 Exception VectorTable0x1C MainLDR PC, [PC,#-0FF0] (VICVectADDR): address of 0x18service routine 0x14 ...Timer-ISRCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 216. VIC - Vectored InterruptsInterrupt 4VICVectAddr4Load PC with Vector AddressISRVICVectAddrCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 217. VIC - Non-Vectored Interrupts InterruptISRVICDefVectAddrISR ISR CODE ISR VICVectAddr ISR ISR Load PC with CommonVector AddressCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 218. VIC - FIQ Interrupt FIQs have higher priority than IRQs– Serviced first– FIQs disable IRQsFIQ Vector is last in vector table (allows handler to be run sequentially from that address) FIQ mode has 5 extra banked registers, r8-12 (interrupt handlers must always preserve non-banked registers) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 219. VIC – FIQ (Fast Interrupt)InterruptFIQ ISR FIQ ISRLoad PC with Vectorin RAM in FlashAddress VectorAddress = 0x1CISR CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 220. Interrupt Prioritizing with NestingIRQ Service Routine of “lower” priority: 1. Push SPSR to LR and on stack2.Switch to System Mode (write CPSR, enable IRQ)3.Push system mode link register on stack4.Execute “real” service routine5.Pop system mode link register from stack6.Switch back to IRQ mode7. Pop SPSR to LR and restore SPSR8. Clear IRQ source9. Reset VIC For Keil compiler, see knowledgebase at www.keil.comCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 221. Hands-OnHands-On Index Tools Setup 1. Oscillator / PLL / MAM / GP I/O 2. ADC 3. Interrupts / Timer 4. UART / CAN 5. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 222. Hands-On Project: BlinkyIRQ Load ProjectBlinkyIRQBuild and DebugSimulation – Use Logic Analyzer• gTimCnt• loop – Peripheral window• Vectored Int. Contr.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 223. Hands-On Exercise: Timer & Interrupt Test and debug in simulator Add timer 1 interrupt tousing: BlinkyIRQ – Performance Analyzer Interrupt all 333us – Signal Analyzer – Peripheral GPIO window Use Vector 1– Peripheral Timer window – Peripheral VIC window In ISR, display some LED pattern on port 1.20 to 1.23 Test program on hardware every 333msCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 224. Hands-OnInterruptsTools Installation 1.• Emulator/Debugger: Emul-ARM Evaluation System(Nohau)• Compiler:Embedded Workbench(IAR)• Flash Tool:Flash ISP Utility (NXP)• Hardware:LPC2106 Target Board(Nohau) Oscillator / PLL 2. Memory Acellerator Module / General Purpose I/O 3. Interrupts 4.a. Single Interruptb. Nested Interrupts UART 5.RTC 6. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 225. Hands-On Single Interrupts (1) IAR Embedded Workbench – Load workspace Chapter 4a File -> Open Workspace -> Chapter 4a_single_Interrupt -> Chapter_4a.eww – Select project Training – Target Debug(= run from RAM!) – Make OK?• Correct error in Timer.c (User Manual !) • Try again CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 226. Hands-On Single Interrupts (2) – Start Seehau (Tools -> Seehau) • Run project (RUN -> Go or Button) – What does Blinkie do in this case?• Browse through source codes – Blinkie_Main.c – Timer.cCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 227. Hands-On Single Interrupts (3)• Browse through source codes – VectorTabDebug.s(Assembler!) Exception Program Vector Table Reset ldr pc,=?cstartup SUPERVISOR mode Undefined ldr pc,=0x0000024 UNDEFINED mode SWI ldr pc,=0x0000028 SUPERVISOR mode Prefetchldr pc,=0x000002c ABORT mode Dataldr pc,=0x0000030 ABORT mode nop reserved → Load contents of the ... IRQ ldr pc,[pc,#-0xff0] IRQ mode ... VICVectAddr. register into PC FIQ ldr pc,=0x1CIRQ mode CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 228. Hands-On Single Interrupts Solution !Timer.c– T0_MCR= 0x03; //Interrupt on Match0, reset timer on match FunctionLEDs are changed whenever variable TimerIsUp=1This variable is • set by Timer 0 interrupt routine after Timer 0 match • cleared by main routine before LEDs are changedCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 229. Hands-On Nested Interrupts (1)IAR Embedded Workbench – Load workspace Chapter 4b File -> Open Workspace -> Chapter 4b_single_Interrupt -> Chapter_4b.eww – Select project Training – Target Debug(= run from RAM!) – Make OK?CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 230. Hands-On Nested Interrupts (2)–Start Seehau (Tools -> Seehau) • Run project(RUN -> Go or Button) – Press SW4 – Release SW4– What does Blinkie do in this case? CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 231. ! Hands-On Nested Interrupts Solution 1 – Two interrupt sources• Timer 0 IR: blinks LEDs• External IR 2 (SW4): stay in ISR until SW4 released – Priorities• External Interrupt > TimerTimer0_ISR()VICVectAddr1Main()⇒ SW4 blocks Timer 0 (LEDs control)ExtInt_ISR() VICVectAddr0– SW2, SW3 change direction (polled in main program)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 232. Hands-On Nested Interrupts (3) – Browse through source codes• Blinkie_main.c• ExtInt.cInitExtInt2()• Timer.c InitTimer0()• VectorTabDebug now initializes SP for differentmodesCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 233. Hands-On Nested Interrupts (4) !– Nested IR-Handler now save status and re-enable further interrupts before entering ISR⇒ nested interrupts possible! Main() Nested IR handlerTimer IRS routineVICVectAddr0Nested IR handlerExt. Int. ISRVICVectAddr1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 234. Hands-On Nested Interrupts (5)– Browse through source codes (cont'd) • NestedIrqHandler.sTimer 0 nestedExternal Interrupt 2 nested save work registers save work registers ExtInt2-pin to GPIO reset IRQ sourcereset IRQ-source switch to System mode, interrupts enabled switch to System mode, interrupts enabled branch to distinct ISRbranch to distinct ISR switch to IRQ mode, IRQ disabledswitch to IRQ mode, IRQ disabled re-enable ExtInt2 reset VIC reset VIC restore work registersrestore work registersCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 235. Hands-On Nested Interrupts (6)– Change priorities: External Interrupt < Timer • Edit Timer.c and ExtInt.c: VICVectAddrn VICVectCntlm InitTimer0() is 1 1 InitExtInt2()is 0 0 InitTimer0() new0 0 InitExtInt2()new1 1Note: lower value (n, m) is higher priority!CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 236. Hands-On Nested Interrupts (7) – MakeOK? – Start Seehau(Tools -> Seehau) • Run project(RUN -> Go or Button) – What does Blinkie do now?CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 237. Hands-On Nested Interrupts! Solution 2– Priorities• External Interrupt < Timer – Blinkie continues, even while SW4 is pressed! – LED5 toggles to indicate recognition of External Interrupt – Two interrupt sources• Timer 0 IR: blinks LEDs• External IR 2 (SW4): stay in ISR until SW4 released (but can be interrupted!) – SW2, SW3 change direction (polled in main program) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 238. Hands-On Nested Interrupts! Solution 2 Timer0_ISR()VICVectAddr0Main()ExtInt_ISR() VICVectAddr1CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 239. Flag(s) VIC IR Source # Block Watchdog Interrupt (WDINT)WDT0Reserved for software interrupts only-1 ARM Core Embedded ICE, DbgCommRx 2VICARM Core Embedded ICE, DbgCommTx 3Match 0 -2 (MR0, MR1, MR2, MR3) Timer 0 4IR SourcesCapture 0 - 2 (CR0, CR1, CR2)Match 0 -3 (MR0, MR1, MR2, MR3) Timer 1 5 Capture 0 - 3 (CR0, CR1, CR2, CR3)UART 0Rx Line Status (RLS)6LPC2104 Transmit Holding Register empty (THRE) Rx Data Available (RDA) LPC2105 Character Time-out Indicator (CTI)LPC2106 UART 1Rx Line Status (RLS)7 Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI)PWM 0 Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8I2C SI (state change) 9SPI SPIF, MODF 10 -reserved 11PLL PLL Lock (PLOCK) 12 RTCRTCCIF (Counter Increment), RTCALF (Alarm) 13 System Control External Interrupt 0 (EINT0) 14 System Control External Interrupt 1 (EINT1) 15 System Control External Interrupt 2 (EINT2) 16 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 240. Flag(s)VIC IR Block Source # add'l ... ... ... VIC SystemExternal Interrupt 3 (EINT3)17 Control IR SourcesA/D Converter A/D 18 * CAN ORed CAN Acceptance Filters 19 * CAN CAN 1 Transmitter 20 LPC2114/24* CAN CAN 1 Receiver21 LPC2119*/29*** CANCAN 2 Transmitter 22 LPC2194** ** CANCAN 2 Receiver23 LPC2210/12/14LPC2 *** CAN CAN 3 Transmitter 24 290**/92***** CAN CAN 3 Receiver25 LPC2294****** CAN CAN 4 Transmitter 26 *** CAN CAN 4 Receiver27plus more flags for UART0, Timer1, Capture 0 - 3 (CR0, CR1, CR2, CR3) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 241. VIC Interrupt Latency Some instructions take multiple cycles to execute and cannot be interrupted – The longest STM and LDM instructions take 20 cycles– Subsets can be reduced to 7 cyclesFIQ: 12 (25) cycles, 200ns (416ns) @ 60MHz First Vectored IRQ (assuming no FIQ pending): 26 (39) cycles, 433ns (650ns) @ 60MHz Default IRQ Vector (assuming no other IRQ pending):42 (55) cycles, 700ns (916ns) @ 60MHzCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 242. Memory Addressing 1. System Control Block 2. Memory Accelerator Module (MAM) 3. General Purpose I/O / Pin Connect Block 4. Vectored Interrupt Controller 5. Integrated Peripherals 6. Timer 0 / Timer 1, UART 0 / UART 1, I²C, SPI, PWM, RTC,Watchdog CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 243. RTC CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 244. Real Time Clock Only forLPC213x,4x LPC23,LPC24PCLK RTCClock Divideroscillator(prescaler)MUXTimeAlarmComparatorsCountersRegisters Clock generator Interrupt GeneratorThe Counter Increment cancause aninterruptCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 245. Real Time Clock Full Clock/Calendar function with alarms– generates its own 32.768 kHz reference clock from any crystalfrequency– counts seconds, minutes, hours, day of month, month, year, day ofweek and day of year– can generate an interrupt or set an alarm flag for any combinationof the counters CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 246. Power consumption of RTC (LPC213x) Core RTCCurrentconsumption fromVbat Power downPower down 20-30µAPower downRunning from 20-30 µA Vbat ActiveRunning around 80 µA(pclk=15MHz)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 247. IAP programming CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 248. 4 ways of programming the LPC2000 FlashIn-Application Programming (IAP)In-System Programming (ISP via NXP Boot Loader, UART0)In-System Programming (through LPC HW macro cells/ and custom software protocol)Parallel programmerCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 249. LPC213x Series Overview FLASH MEMORY– ISP: In-System programming is programming or reprogramming the on-chip flashmemory, using the boot loader software and a serial port. This can be done whenthe part resides in the end-user board.– IAP: In-Application programming is performing erase and write operation on theon-chip flash memory, as directed by the end-user application code.– User-code security : Code read protection is enabled by programming the flash addresslocation 0x1FC (User flash sector 0) with value 0x87654321 (2271560481 Decimal).Disabled: • JTAG debug port • External memory boot • Following ISP commands:Read MemoryWrite to RAMGoCopy RAM to Flash CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 250. ADC CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 251. A/D Converter Features– 10 bit successive approximation analog to digital converter– Multiplexed inputs• 4 pins(64-pin devices)• 8 pins(144-pin devices)– Power down mode– Measurement range 0V ... 3V– Minimum 10 bit conversion time: 2.44 µS– Burst conversion mode for single or multiple inputs– Optional conversion on transition on input pin or Timer Match signal– Programmable divider to generate required 4.5MHz from VPB clockCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 252. A/D Converter – Burst modeCLKS: bit 17, 18, 19 of ADCR select the number of clocks used per conversion and the accuracy– 000b: 11 clocks, 10 bits– 001b: 10 clocks, 9 bits– 010b: 9 clocks, 8 bits– 011b: 8 clocks, 7 bits–…– 111b: 4 clocks, 3 bitsCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 253. ADC LPC213X, LPC214X Separate result register for each channel – Reduces the interrupt overhead by a factor of 8 Measurement range of 0 V to 3 V – Separate voltage pins for analogue 3V supply (V3A) and analogue ground (VSSA) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 254. ADC – Software Controlled ModeAll conversions are 10-bit and take 11 clocks4.5Mhz Maximum ClockAllows conversion to start on an external edgeADC Inputs 7 65 43210ADDR0ADDR1 10-bit ADCSelect Single Channel ADCR (7:0) (11 Clocks/Conv) ADDR7 V3A VSSACONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 255. ADC – Burst ModeResult accuracy and speed are programmableInput selected by the SEL bits are scanned ADC Inputs ADC Clock(CLKS Bits)1-8n-bit ADCSelect Multiple Channels Input Scan ADCR (7:0) (n Clocks/Conv)(SEL Bits) ADDR7 ADDR0 ADDR1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 256. DAC CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 257. LPC213x Series Overview DAC (10-bit)This peripheral is available in the LPC2138 only. The D/A converter enablesthe LPC2138 to generate variable analog output. • 10 bit digital to analog converter • Resistor string architecture • Buffered output • Power down mode • Selectable speed vs. power CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 258. LPC213x DAC Digital-to-Analog Converter (DAC) – 10-bit resolution DAC with a buffered output• Last output value is held as long as DAC is on – Output from Zero Volt to Reference Voltage• In 1024 steps – Selectable Conversion speed vs. power• Settling time 1us, up to 350uA• Settling time 2.5us, up to 700uA – Selective power downCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 259. Hands-OnHands-On Index Tools Setup 1. Oscillator / PLL / MAM / GP I/O 2. ADC 3. Interrupts / Timer 4. UART / CAN 5. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 260. Hands-On Project: BlinkyADC Load ProjectBlinkyADCBuild and DebugSimulation – Use Logic Analyzer – Peripheral windows• GPIO P1• ADC -> modify voltage Run on hardware – Verify change of AD values with potentiometerCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 261. UARTCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 262. Serial Communication InterfacesTwo UARTs 10100101 10110110 01111000 I2C 0010000010 11 SPI 01 01CAN SSP01010010110110110CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 263. UART0 / UART1 TxD0UART 0 InterfaceRxD0TxD1CTSDTRUART 1RxD1ModemDCD Interface InterfaceRIsignalsRTSDTR Maximum possible speed of the UART 3.75 Mbits/secCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 264. UART0 / UART1Register locations conform to ‘550’ industry standard UART Built-in Baud Rate Generator– 16-bit baud rate generator clock divisor made from 2 8-bit divisorregisters: DLM (MSB), DLL (LSB)– Required baud rate: pclk / (16 x Divisor*)(* if the Divisor is 0x0000, it is treated as 0x0001.)– Fractional baud rate generator (LPC214x, LPC2101-2-3)Error Detection– Parity, Framing and Overrun Errors detected– Break Interrupt detectionCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 265. UART0 / UART1 (cont.) 16 byte Receive and Transmit FIFOs– Receive FIFO trigger points at 1, 4, 8, and 14 bytes– Break signal can be transmittedWord Length Select: 5, 6, 7 or 8-bit characters Stop Bit Select: 1 or 2 stop bits Parity Select: Odd or Even parity Supports 6 modem control signals• CTS, RTS, DCD, DSR, DTR and RI functions are selectable• Note:On 48-pin devices UART 0 has Tx and Rx pins onlyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 266. IIC CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 267. I2C Bus Interface(s) SDAI2C Interface1 SCLSDA 2nd I2C interfaceI2C on LPC213xInterface2 SCL Maximum possible speed of the I2C 400Kbits/secCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 268. I2C BusFast-I2C compliant bus interface– configurable as Master, Slave, or both– multi-master bus– bi-directional data transfer between masters and slaves– up to 400kb/s– arbitration between simultaneously transmitting masters withoutcorruption of serial data on the bus– serial clock synchronization allows devices with different bit rates tocommunicate via one serial bus– programmable clock rate CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 269. SPI Interface MISOMOSI SPIInterfaceSPICLKSS Maximum possible speed of the SPI 7.5 Mbits/secCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 270. SPI Bus Compliant with Serial Peripheral Interface (SPI) specification Combined SPI master and slave function Maximum data bit rate of 1/8 of the peripheral clock rate Programmable clock polarity and phase for data transmit/receive operations No. of SPI channels:–1(48-pin devices)–2(64/144-pin devices)CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 271. SSP CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 272. Serial Synchronous Port (SSP) InterfaceMISO1MOSI1SSP InterfaceSCK1SSEL1 Maximum possible speed of the SSP 30 Mbits/secCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 273. SSP Interface Compatible with Motorola SPI, 4-wire TI SSI andNational Semiconductor Microwire bus Supports multiple slaves and master on the bus butat any point of time only one master and slave cancommunicate 8-Frame FIFO’s for both Transmit and Receive Frame sizes can be from 4 bits to 16 bits CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 274. USB CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 275. USB 2.0 Since USB is a standard doesn’t that make allmicrocontrollers with USB the same? NO!!Architectural choices and implementation details make a bigdifference in performance and ease of use. The LPC2148 is a high performance USB device. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 276. LPC2148 key high performance USB features Flexible endpoint architecture – Supports all 32 USB endpointsLarge data FIFO – Can double buffer full isochronous packetsFlexible DMA capability – USB Buffer is present on the AHB bus CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 277. Introduction to USB An Auto-configuring Plug-and-playSerial Bus HOST/HUBPC Single Master, Half-duplex, Time-HUBmultiplexed bus; Tiered StarPhone Monitortopology HUB Kbd All data communication is initiated SpeakerMicand regulated by the Master; peer-Mouse Pento-peer not allowedUSB 2.0 is the latest version of USB(downward compatible) CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 278. USB- A Brief History USB 1.1USB 2.0OTGApproved on 11/23/99 Original USB 2.0 Supplements the 2.0by the USB Core team specification released specification12 Mbps bus on April 27, 2000Connects peripheralsFull-speed (12 Mbps) 480 Mbps bus directly to each otherLow-speed (1.5 Mbps) High-speed (480 Mbps)New mini-A connectorStandard A connectorand mini-AB Full-speed (12 Mbps)and standard Breceptacle Low-speed (1.5 Mbps)connector Backward compatible with USB 1.1 New mini-B connector CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 279. USB Connections and TerminationsR2 D+ D+F.S./L.S. USB F.S. USB TransceiverR1 Transceiver Twisted Pair Shielded D- (45 ohms Outputs)(45 ohms Outputs) D-ZO = 90 ohms±15%5 Meters Max. Hub Port 0 R1Host orR1 = 15K ohm±5% orHub Port R2 = 1.5K ohm±5%Full Speed FunctionD+ D+F.S./L.S. USB L.S. USB TransceiverR1 Transceiver Untwisted, UnshieldedR2 D- (45 ohms Outputs)(45ohms Outputs)3 Meters Max. D-R1R1 = 15K ohms±5%Host or Low Speed Function R2 = 1.5K ohms±5%Hub Port sb.orgwww.usb.org www.usb.orgwww.usb.orgwww.usb.orgwww.usCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 280. Device Layers Function – Represents capability delivered by the device, The primary „usage“ function,Function like mouse, audio output, printer, hub, etc. USB Logical Device – Defines common view of device by host USB Logical USB Logical – Manages high-level protocol Device Device – Typically controlled by system software – May have multiple functions with multiple endpointsUSB BusUSB Bus InterfaceInterface – Physical interface to wire – Manages low-level protocol CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 281. Device Abstractions End Point – Ultimate data source or sink at the device end – Unique address, unidirectional, transfer characteristics – Each endpoint is unidirectional and has a transfer type associated with its peripheralPipe – Association of endpoint with host SW ownerInterface – Collection of pipes – Map to a capability – Owned by exactly 1 software client – More that 1 interface can be defined in a device CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 282. Endpoints Up to 32 (16 pairs) endpoints can reside within a device – All USB transfers are targeted to/from a device endpoint – An endpoint is a buffer used to transmit or receive data Each endpoint has a direction and an address – The direction is from the host’s perspective • OUT transactions are to the device • IN transactions are from the deviceA Control endpoint contains an IN and OUT endpoint – Endpoint 0 is always the Control endpointCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 283. Interfaces Made of 0 or more pipesHas a client owner – Accesses individual pipes – Shares default pipeMore dynamically configured than devices CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 284. Pipes Connect host memory buffer to endpoint FIFOStream Type – No USB imposed data format – UnidirectionalMessage Type – USB imposed data format – BidirectionalCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 285. Detailed Host / Device ViewHost DeviceFunctionClient SWa collection of Interface xmanages an interface InterfacesPipe Bundle No USB InterfaceNo USBto an interfaceBuffersFormat SpecificFormatUSB Device USB System Endpoint a collection of manages devicesZero endpointsDefault Pipeto Endpoint ZeroUSBUnspecified Data PerData FramedEndpoint Data USB BusUSB BusHostInterface InterfaceController USB Framed Data SIESIETransactionsUSB WireEndpoint 0 Pipe, represents connectionabstraction between two horizontal layers - Required, shared Data transport mechanism - Configuration accessUSB-relevant format of transported data - Capability controlCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 286. Client Software <-> Function HostHostClientClient Software Software BuffersBuffers Data Flows Data Flows Pipes PipesEndpoints EndpointsUSB DeviceUSB Device Interface Interface CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 287. Communications Layers PhysicalPacketsTransactions – 3 phases (token, data, handshake) – Token phase has token packet sent by host • Always present • Packet ID (PID) identifies transaction type – Other phases have 0 or more packetsTransfers CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 288. Transfers to Transactions InterfaceInterface InterfaceInterfaceInterface Interface PipePipe Pipe Pipe Client SWClient SWPipePipe DeviceDeviceDescriptionDescription Device Device Device Device DeviceDevice Driver Driver Driver Driver DriverDriverService Service UserDescription UserDescriptionParamsParams USB System SW Transfer ManagerUSB System SW Transfer Managerand and Host ControllerTransactionHost ControllerTransactionListList Requirements,Limitations TransactionSchedule TransactionScheduleExecutorExecutorToken Token TokenToken Token Token Universal Serial BusCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 289. USB Protocol – Breakdown Transfer Types • ControlTransfer • Interrupt • Bulk • Isochronous Transaction TypesTransactionTransaction • OUT • IN • SOF (Start of Frame) • SETUP Token PacketData Packet Handshake Packet• PID – Packet IDentifier (16 types) • Body – Depended on Packet type • CRC – Cyclical Redundancy CheckPIDBody CRC used for error checking CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 290. FramesFull / Low Speed Frame Size (1 ms) 1 ms1 ms 1 msControl SOF packets Isochronous marks each Interruptframe tick BulkCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 291. Data Transfer Types Comparison Control InterruptBulk Isochronous Usage Max Data bytes/msec 24 bytes (three 8-byte 0.8 bytes (8-bytes per 10 in low-speed mode transactions)msec)no support no supportMax Data bytes/msec 832 (thirteen 64-byte 64 (one 64-byte1216 (nineteen 64-byte 1023 (one 1023-byte in full-speed mode transactions/frame)transaction/frame)transactions/frame)transaction/frame) Error Correction yesyes yesno Guarantee rate of delivery no nonoyes Guranteed time between transfersnoyes no yes Typical usesConfigurationMouse, keyboardPrinter, scannerAudio, video Note: frame = 1msec @FSCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 292. USB Frame Model Slot Frame = 1msBULKLow SpeedStereo AudioLow SpeedStereo Audio BULKBULKStereo Audio BULKStereo Audio BULKStereo Audio BULKStereo Audio BULKStereo Audio BULKStereo Audio BULKStereo Audio BULKStereo AudioLow Speed (not to scale) Rx VoiceTx VoiceSOF Interrupt, ScannerRx LineTx Line Control,CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 293. Transactions Transactions are always initiated by the Host and therefore thought offrom the Host’s perspectiveA Transaction consist of multiple packets and begin when the hostsends one of four Token Packets – OUT – notifies the DC that data is being send “out” from the Host – IN – requests that DC send data “in” to the Host – SOF – signals the “Start of Frame” – SOF – signals the “Start of Frame” A Data Packet follows the token packetThe Transaction ends with Handshake Packet to report the Status ofthe Transaction. CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 294. Packet Formats11 bits 5 bits 8 bits SOF PacketPIDFRAME NUMBERCRC57 bits4 bits5 bits 8 bitsToken PacketADDR ENDPCRC5 PID 0 – 1023 bytes 16 bits 8 bitsData PacketPIDPAYLOAD CRC16 8 bits Handshake PacketPID CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 295. Endpoints in LPC2148 Maximum of 32 (16 logical) endpointsSelectable Double Buffering for Bulk andIsochronous Data TransferAny combinations of Endpoints allowedMaximum buffer size supported for all endpointstypesCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 296. USB 2.0 in LPC2148 Fully Compliant with USB 2.0 SpecSupports 32 physical endpointsScalable realization of Endpoints during run timeDouble buffering supported for Bulk and IsochronousEndpointsSupports DMA transfer on all non-control endpoints CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 297. USB 2.0 in LPC2148 Supports Control, Bulk, Interrupt and Isochronous endpointsSupports SoftConnect featureSupports Good link LED indicatorFlexible clock architectureRemote wakeup CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 298. LPC2148 USB Block DiagramAHB BusUsing the DMA, the8K AHBUSB Logic has directMemory access to memory DMAEngineVPB Bus ATXUSB LogicPADS D+ Force SE0 TX D OE D-Endpoint ram Serial Interface Engineaccess control (SIE)RegisterInterface RX D2K FIFO ReceiversCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 299. Transfer Modes Slave Transfer ModeDMA Transfer ModeCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 300. Slave Mode Transfer USB Block acts like a slaveIt can only issue interrupts to the CPUControl EP uses this mode of transfer exclusivelyCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 301. DMA Mode Transfer USB Block acts like a MasterWill transfer data directly from the 8K SRAM to theEP_RAM and vice versa.For Isochronous transfers, the DMA transfer issynchronized to the frame interruptCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 302. Soft Connect and Good Link™ LED Soft Connect – Can connect/re-connect to the host through software – No need to unplug and plug the cable back againGood Link™ LED – Needs a shared GPIO pin – Shows indication on a LED if connection is established CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 303. LPC2148 connections3.3 volt system power Vusb bus sense Logic level p channel FETGood LinkLPC2148 Philips BSH203 Soft connect_n1.5k Vusb supplyD-33 D-ATX33Pad D+ D+CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 304. LPC2148 Clock ArchitectureLPC2148 clocks Main cclkXTAL PLLVPB clock must be 16 MHz VPBpclk minimum for the USB vpb interfacedivider USBUSB clk PLLCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 305. CAN CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 306. NXP LPC2000 Series CAN Controller Extended Full CAN Controller 2 or 4 CAN interfaces 3 priority controlled transmit buffers per channel Global filter and buffer system with up to 1024 filters Status/ControlCAN RegistersBusBus InterfaceCANTransmit TransmitProtocol Buffer 1 TransmitBuffer 2Controller Buffer 3 Global AcceptanceHostHost CPUFilter Table with up Inter- to 1024 filters; faceCANbuffered inBus InterfaceBus“Full CAN” modeCANProtocol TransmitController Transmit Buffer 1 TransmitBuffer 2 Buffer 3 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 307. LPC CAN controller and SJA1000 Each CAN Controller has a register structuresimilar to the NXP SJA1000 and the PeliCANLibrary block, but the 8-bit registers of thosedevices have been combined in 32 bit words toallow simultaneous access in the ARMenvironment. The main operational difference isthat the recognition of received Identifiers, knownin CAN terminology as Acceptance Filtering, hasbeen removed from the CAN controllers andcentralized in a global Acceptance Filter.CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 308. CAN Bus Baud Rate and Bus LengthUp to 1Mbps @ 40m bus length (120 feet)ORUp to 1000m bus length (3000 feet) @ 50 kbps1000Bus lines assumed to be500an electrical 200medium 100Bit Rate(e.g.twistedpair)50 [kbps]2010 5 0 10 40 100 200 1000 10,000 CAN Bus Length [m]CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 309. CAN Bus (1)CAN (Controller Area Network) features– Serial communications protocol– Efficiently supports distributed real-time control– Very high level of security– Application domain: high speed networks to low cost multiplex wiringLPC2xxx with CAN have 2 or 4 CAN channels– Can be used as gateway, switch or router among CAN buses– Industrial or automotive applications CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 310. CAN Bus (2)Data rates to 1 Mbit/s on each bus 32-bit register and RAM access Compatible with CAN specification 2.0B, ISO 11898-1 Global Acceptance Filter recognizes 11- and 29-bit Rx Identifiers for all CAN buses Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers No. of CAN channels– 2 on LPC2119, LPC2129, LPC2290, LPC2292– 4 on LPC2194, LPC2294 CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 311. CAN Bus (3) Acceptance Filtering• Recognition of received Identifiers (Acceptance Filtering) removedfrom CAN controllers - now centralized in a global AcceptanceFilter• In a 2KB RAM (512 x 32) software maintains 1 ... 5 tables ofIdentifiers RAM can hold up to 1024 Standard Identifiers or 512Extended Identifiers, or a mixture of both types CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 312. •TIMERS •PWMs •RTC •WATCH-DOGCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 313. Timer 0 and 1 32-bit Timer 32-bit Capture Registers and Capture Pins– Four on each timer (48-pin devices three on Timer 0 and four on Timer 1) – Capture event can optionally trigger an interrupt32-bit Match Registers and Match Pins– Four on each timer (48-pin devices three on Timer 0 and four on Timer 1) – Interrupt, timer reset or timer halt on match– Match output can toggle, go high, go low or do nothing CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 314. Timer CaptureControl Capture Control RegisterCapture Input 0Interrupt Register Capture Input 1Timer Control Register ENABLE RESET Capture Input 2Capture Register 0 Capture Input 3*Capture Register 1 32-bit Timer/Counter LoadCapture Register 2 Capture Register 3* 32-bit Pre-Scaler Interrupt PCLK *: not available in 48-pin devicesCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 315. Timer Compare Match Control Register Control External Match RegisterMatch Output 0 Interrupt RegisterMatch Output 1Match Register 0Match Output 2Match Register 1Timer Control RegisterMatch Output 3*Match Register 2 ENABLE RESETMatch Register 3Interrupt 32-bit Timer/Counter= Timer=MR3= Timer=MR2 *: not available in 32-bit Pre-Scaler= 48-pin devicesTimer=MR1= PCLK Timer=MR0 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 316. Pulse Width ModulatorDedicated 32-bit PWM timer– similar functionality to Timer0 / Timer1Three additional match registers for a total of 7– all PWM outputs have the same rate, which is programmable– allows up to 6 single edge controlled or 3 double edge controlledPWM outputs in any combination– single edge controlled PWM outputs all go high at the beginning ofeach cycle and low at a programmed time– double edge controlled PWM outputs can be programmed to beeither positive going or negative going pulses, with edges at anylocation in the cycleCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 317. Pulse Width Modulator Match Register 0Match Latch Enable 0=Shadow Register 0QSPWM1 = EnableR ENInterruptQS PWM2 = EnableR ENControl32-bit Timer Counter32-bit Pre-ScalerQS PWM6 Enable= R EN PCLKCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 318. Single-Edge Controlled PWM PWM outputs all go high at the beginning of each cycle andgo low on a MatchMatch Register 0 Value Compare (Match) Value z er im e Compare (Match) Value y TulVa Compare (Match) Value x 0000 0000h PWMxPWMyPWMz CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 319. Double-Edge Controlled PWMDouble edge controlled PWM outputs can have either edgeoccur at any position within a cycle Match Register 0 Value (100) (PWM Period) MR5=65 (PWM5) MR3=53, MR4=27 (PWM4) MR1=41, MR2=78 (PWM2) rTimee0000 0000h Valu PWM2 PWM4 PWM5 (single-edge) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 320. Hands-OnHands-On Index Tools Setup 1. Oscillator / PLL / MAM / GP I/O 2. ADC 3. Interrupts / Timer 4. UART / CAN 5. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 321. Hands-On Project: SerialRTCLoad Project SerialRTC Build and Debug Simulation– Use Serial Window #2Target Hardware– Use terminal programset to 9600bps CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 322. Watchdog TimerOnce activated, the Watchdog will reset the entire chip if it is not fed regularly Feed is accomplished by a specific sequence of data writes Watchdog flag allows software to tell that a watchdog reset has occurred Selectable overflow time (µs ... minutes) Debug Mode generates an interrupt instead of a reset Secure: watchdog cannot be turned off once it is enabled Watchdog Timer value can be read in one cycleCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 323. Watchdog TimerWatchdog TimerWDFEED Constant PCLK 32-bit Down Counter/4UNDERFLOW Current Timer Count (WDTC)WDMOD Register WDEN WDTOFWDINT WDRESET Sticky bits!RESET(cleared by WDTINTERRUPT underflow or ext. reset) CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 324. NXP LPC2300/2400 Selected PeripheralsClock treeCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 325. Clocking (only for LPC23/24 families) usbclkUSB1-24MHz(48 MHz) ClockUSB Block DividerMain OscillatorPLL CPUFccopllclk cclkARM7TDMI-S Clock Divider system Bypass25 orExternalclock selectEthernetSynchro-50 MHzEthernetnizerBlockPHYInternalR/C 4MHz OscillatorOther AHBWatchdog wdclk Peripherals Timer Perpipheral Clock Generator watchdogclock select pclk APB PeripheralsRTCPrescaler32.768kHzReal Time rtcclk RTCClock OscillatorRTC clock selectCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 326. PLL details on LPC23/24 CCK or CCLK/2 or CCLK/4 1..128Fcco = 275-550 MhzFosc: 32Khz – 50Mhz M = 1…32768 N = 1..256CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 327. LPC23/24 clocking The LPC2300 has three clock sources – External oscillator 1Mhz – 24 Mhz – External watch crystal 32.756 Khz – Internal RC oscillator approx 4 MhzThe LPC2300 has three clock sources Fcco = (2 x M x Fin)/N – Were 32Khz < Fin < 50Mhz – Were 275Mhz < Fcco < 550Mhz – Also Fcco must be kept to a minimum to reduce power consumption– The USB peripheral requires a precise 48Mhz clock source CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 328. NXP LPC2300/2400 Selected PeripheralsLPC2300 Peripherals – SD/MMCCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 329. LPC2300 Peripherals – SD/MMCConformance to Multimedia Card Specification v2.11. Conformance to Secure Digital Memory Card Physical LayerSpecification, v0.96. Use as a multimedia card bus or a secure digital memory card bushost. It can be connected to several multimedia cards, or a singlesecure digital memory card. DMA supported through the General Purpose DMA Controller.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 330. LPC2300 Peripherals – SD/MMC Multimedia Card Interface MCICLK ControlMCIPWRUnit MCICMD Command PathAPB AdapterAPB BusInterfaceRegisters MCIDATA [3:0] Data Path FIFOCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 331. LPC2300 Peripherals – BASIC TRAINING SD/MMC/SDIO CONFIDENTIAL 331 Subject/Department, Author, MMMM dd, yyyy
  • 332. LPC2300 Peripherals – SD/MMC SD/MMC memory card interface (LPC2368 & LPC2378) Conformance to Multimedia Card Specification v2.11.Conformance to Secure Digital Memory Card Physical LayerSpecification, v0.96.Use as a multimedia card bus or a secure digital memory card bus host.It can be connected to several (~4 based on I/O pin loading) multimediacards, or a single secure digital memory card.DMA supported through the General Purpose DMA Controller. ORCONFIDENTIAL 332Subject/Department, Author, MMMM dd, yyyy
  • 333. LPC2300 Peripherals – SD/MMC BASIC TRAINING SD “Secure Digital” (LPC23xx = 25Mbit/s) – Developed as improvement on MMC – Up to 128 Gbyte per card – Low speed up to 400Kbit/s – High speed up to 100Mbit/s MMC “Multi-Media Card” (LPC23xx – 20Mbit/s) – 1, 4, or 8 bits per interface – Up to 8Gbyte per card – Slightly thinner than SD cards – Pin-compatible with SD cards SDIO – small devices that use the SD physical format for other functions beyond storage – GPS, WiFi, BlueTooth, Modems, FM Radio, RFID, Barcode, etc., etc. – Additional interconnect functionality required – May require interrupt line (SD interface does not provide)http://en.wikipedia.org/wiki/Secure_Digital_cardCONFIDENTIAL 333Subject/Department, Author, MMMM dd, yyyy
  • 334. I2S FeaturesThe I2S input and output can each operate independently in both master andslave mode. Capable of handling 8, 16, and 32 bit word sizes. Mono and stereo audio data supported. The sampling frequency can range (in practice) from 16-48 kHz. Word Select period in master mode is configurable (separately for I2S inputand I2S output). Transmit and receive functions each have an 8 byte data FIFO. Programmable FIFO level interrupts. Two DMA requests, controlled by programmable FIFO levels. Controls include reset, stop and mute options separately for I2S input and I2Soutput. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 335. I2S DiagramsSCK: serial clock SCK: serial clockTransmitter Receiver TransmitterReceiverWS: word select WS: word select (master)(slave) (slave)(master)SD: serial data SD: serial data Controller(master)SCKTransmitterReceiver WS(slave) (slave) SDSCKWSSD MSBLSBMSB Word n-1Word nWord n+1Right Channel Left ChannelRight ChannelCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 336. NXP LPC2300/2400 EthernetCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 337. External Memory Controller, ARM PrimeCellTMSDR SDRAM memory support.Asynchronous static device support including RAM, ROM, and Flash.Low transaction latency.Read and write buffers reduce latency and improve performance.8-bit, 16-bit, and 32-bit wide static memory support.Static memory features include:– Asynchronous page mode read.– Programmable wait states.– Bus turnaround delay.– Output enable, and write enable delays.– Extended wait.Four chip selects each for SDRAM and static devices.Power-saving modes dynamically control CKE and CLKOUT.Support for dynamic memory self-refresh mode.Supports 2K, 4K, and 8K row address synchronous memory parts.– Typically 512, 256, and 128 MB parts with 4, 8, 16, or 32 bits per device.Separate reset domains allow for auto-refresh through chip reset.CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 338. External Memory Controller Block Diagram EMC A[23:0] SharedD[31:0]Signals WEn OEn Data AHB slave StaticBuffers registerMemoryBLSn[3:0]interfaceSignals AHB BusCSn[3:0] PadInterface Memory AHB slave controller memorystateDYCSn[3:0]interfacemachineCASn RASn Dynamic MemoryCLKOUT[1:0] SignalsCKE[3:0] DQM[3:0] CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 339. Advanced Vectored Interrupt Controller,Standard ARM PrimeCellTM Mapped to AHB address space for fast access. Supports 32 vectored IRQ interrupts. 16 programmable interrupt priority levels.Fixed hardware priority within each programmable priority level. Any input can be assigned as an FIQ interrupt. Software interrupt generation. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 340. Vectored Interrupt Controller Interrupt Request, Masking, and SelectionSoftIntClear IntEnableClear[31:0] [31:0]Status Registers and FIQ GenerationSoftInt IntEnableFIQStatus[31:0][31:0] [31:0]FIQ FIQStatusVICINT [31:0] SOURCE IRQStatus [31:0] [31:0]IRQStatus [31:0]RawIntrIntSelect[31:0][31:0] Prioritization and Vector Generation Vectored Interrupt 0 SW PriorityM ask [31:0] SW PriorityM ask IRQStatus[0][31:0]DQD QHW PriorityM ask [31:0]PriorityVectIRQ0SW PriorityM ask [0] MaskingHW PriorityMask [0]Logic IRQPriorityVectPriority0Vect Addr0 Logic [31:0]VectAddr0[4:0][31:0] Vector Selectfor highest priority Vectored Interrupt 1 VectIRQ1 interrupt IRQStatus[1]Vect Addr1 [31:0] VectAddrOut VectAddr[31:0] Vectored Interrupt 31 VectIRQ31 IRQStatus[31] Vect Addr31[31:0] CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 341. DMA (1) Two DMA channels, each with a four-word FIFO.16 peripheral DMA request lines. Some of these are connected to peripheralfunctions that support DMA: the SD/MMC, two SSP, and I2S interfaces.One 32-bit AHB bus master interface.Single DMA and burst DMA request signals. Each peripheral connected to theGPDMA can assert either a burst DMA request or a single DMA request.Memory-to-memory, memory-to-peripheral, peripheral-to-memory, andperipheral-to-peripheral transfers are supported. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 342. DMA (2)Scatter or gather DMA is supported through the use of linked lists.Hardware DMA channel priority: channel 0 is higher priority than channel 1.Incrementing or non-incrementing addressing for source and destination.Programmable DMA burst size.8, 16, and 32-bit wide transactions.Big-endian and little-endian support. Little-endian is the default.An interrupt can be generated on a DMA completion or error.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 343. GPIO InterruptsGPIOIntStatRising Edge Port Int GPIOIntStatusAPB R RegisterEnable RegisterRegisterVICBus(Read Only) (GPIOIntEnR)Interrupt 1DQOther Port Ints GPIOPinplus one existingPin RIntinterruptWrite 1 toPortGPIOIntClr WakeupR Wakeup1DQ OtherPin IntsGPIOWakeFalling Edge GPIOIntStatFOther PortAPB (from IntWakeEnable RegisterRegisterWakeupsBusRegister) (GPIOIntEnF)(Read Only)Replicated for each Replicated for eachOnce per chiprelated GPIO pinrelated GPIO portCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 344. Ethernet MAC – System ConnectionsSignals TRST Trace Xtal1 Xtal2TDOTMS RSTTCKTDISystemTest/Debug Interface 64 KB512 KB Emulation TracePLL Functions SRAMFlashModuleARM7TDMI-SSystem Internal RC ClockOscillator Internal InternalSRAM Flash A[23:0],Controller ControllerD[31:0],Vectored External 16 KB etc.InterruptMemory ARM7 Local BusSRAMController ControllerAHB AHBBridgeBridgeAHB2 AHB1MII D+, D-, AHB toEthernet USB withorMasterSlave16 KB GP DMAetc. Port AHB Bridge RMII PortMAC with 4KB RAMSRAMController DMA& DMA APBAHB toDivider APB Bridge APBCONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 345. Ethernet Block DiagramInterface Transmit HostBus Flow Registers RMII adapter Register ControlRMII Interface (AHB slave) AHB BusEthernet MAC TransmitTransmit DMARetry Bus Interface MII orEthernet PHY RMIIMII DMA Receive Receive InterfaceDMA Buffer (AHB master)MIIM ReceiveFilterEthernet Block CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 346. Ethernet Basic Features General: – 10/100MBps Ethernet MAC – PHY interface, including MII and RMII (on LPC2300 RMII only)• List of recommended devices in datasheet– Internal scatter/gather DMA controller – Semi-dedicated 16K byte on-chip RAM – Can access other memory areas (including off-chip) except the Flash and main SRAMCONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 347. Ethernet Features: Standards Ethernet standards supported: – Supports 10 or 100 Mbps PHY devices including 10Base-T, 100Base-TX, 100 Base-FX, and 100Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – VLAN frame support.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 348. Ethernet Features: Memory Transfers Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 349. Ethernet Advanced Features Receive filtering.Multicast and broadcast frame support for both transmit and receive.Optional automatic FCS insertion (CRC) for transmit.Selectable automatic transmit frame padding.Over-length frame support for both transmit and receive allows anylength frames.Promiscuous receive mode.Automatic collision backoff and frame retransmission.Includes power management by clock switching.Wake-on-LAN power management support allows system wake-up:using the receive filters or a magic frame detection filter.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 350. Ethernet Features: Physical Layer Physical interface:– Attachment of external PHY chip through standard Media IndependentInterface (MII) or standard Reduced MII (RMII) interface, softwareselectable.– PHY register access is available via the Media Independent InterfaceManagement (MIIM) interface.NOTE: LPC23xx has RMII only CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 351. PHY Interface – MIIM (Media Independent Interface Management)MIIM Pin # of Pins FunctionMDC 1Clock Combined data input, data output, and data output MDIO 1enable. The protocol defines how and when the direction changes.Total: 2 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 352. PHY Interface – MII (Media Independent Interface)MII Pin# of Pins Function TX_EN 1Transmit data enable TXD[3:0]4Transmit data output TX_ER 1Transmit error TX_CLK1Transmitter clockCOL1CollisionCRS1Carrier sense RX_DV 1Receive data validRXD[3:0] 4Receive data input RX_ER 1Receive error RX_CLK1Receiver clockTotal: 16 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 353. PHY Interface – RMII (Reduced Media Independent Interface)RMII Pin # of Pins Function TX_EN1Transmit data enableTXD[1:0]2Transmit data outputRXD[1:0]2Receive data inputCRS_DV1Carrier sense / Data valid RX_ER1Receive error (optional, depending on application)REF_CLK 1Reference clock inputTotal:8CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 354. CAN Interface incompatibilities within LPC2000 derivatives To conserve power, CAN peripherals are powered down after reset onthe latest derivatives – Code must manually enable the power for the CAN interfaces usedWhen using the filter tables, the numbering of CAN interfaces might vary – In some implementations CAN interfaces are numbered 1 and 2 – In some implementations CAN interfaces are numbered 0 and 1 CONFIDENTIAL Subject/Department, Author, MMMM dd, yyyy
  • 355. Other Peripherals USB with Device, Host, and OTG.UARTs (4), one with modem control, one with IrDA.CAN (2 channels).SD / MMC Card Interface.SPI (1) & SSP (2). SPI shares pins with SSP0.Timers (4), each with capture/compare.Watchdog Timer.DAC output.CONFIDENTIALSubject/Department, Author, MMMM dd, yyyy
  • 356. Thank You!
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